William A. Rogers

According to our database1, William A. Rogers authored at least 18 papers between 1985 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

1999
A cost-effective design for testability: clock line control and test generation using selective clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1994
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Hierarchical test pattern generation: a cost model and implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
A test methodology for finite state machines using partial scan design.
J. Electron. Test., 1992

A Synthesis Algorithm for Two-Level XOR Based Circuits.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
STarS: a target switching algorithm for sequential test generation.
Proceedings of the 9th IEEE VLSI Test Symposium (VTS'91), 1991

The Impedance Fault Model and Design for Robust Impedance Fault Testability.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
Search strategy switching: A cost model and an analysis of backtracking.
J. Electron. Test., 1990

1989
Generating Single-Stuck-Fault Coverage from a Collapsed-Fault Set.
Computer, 1989

Search Strategy Switching: An Alternative to Increased Backtracking.
Proceedings of the Proceedings International Test Conference 1989, 1989

FANHAT: fanout oriented hierarchical automatic test generation system.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
PhD thesis, 1988

Fault Simulation in a Distributed Environment.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986
Structured Functional Level Test Generation Using Binary Decision Diagrams.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
Proceedings of the Proceedings International Test Conference 1985, 1985

High level hierarchical fault simulation techniques.
Proceedings of the 13th ACM Annual Conference on Computer Science, 1985


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