Sanghyeon Baeg

According to our database, Sanghyeon Baeg authored at least 38 papers between 1994 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Write Recovery Time Degradation by Thermal Neutrons in DDR4 DRAM Components.

Hyeongseok Oh, Myungsun Chun, Jiwon Lee, Shi-Jie Wen, Nick Yu, Byung-Gun Park, Sanghyeon Baeg

Proceedings of the IEEE International Reliability Physics Symposium, 2023

2021

Exploitations of Multiple Rows Hammering and Retention Time Interactions in DRAM Using X-Ray Radiation.

Donghyuk Yun, Myungsang Park, GeunYong Bak, Sanghyeon Baeg, Shi-Jie Wen

IEEE Access, 2021

DDR4 Data Channel Failure Due to DC Offset Caused by Intermittent Solder Ball Fracture in FBGA Package.

Muhammad Waqar, GeunYong Bak, Junhyeong Kwon, Sanghyeon Baeg

IEEE Access, 2021

Fault Coverage Re-Evaluation of Memory Test Algorithms With Physical Memory Characteristics.

Kiseok Lee, Jeonghwan Kim, Sanghyeon Baeg

IEEE Access, 2021

2019

Architectural design tradeoffs in SRAM-based TCAMs.

Ali Ahmed, Kyungbae Park, Saqib Ali Khan, Naeem Maroof, Sanghyeon Baeg

IEICE Electron. Express, 2019

2018

Study of proton radiation effect to row hammer fault in DDR4 SDRAMs.

Chul Seung Lim, Kyungbae Park, GeunYong Bak, Donghyuk Yun, Myungsang Park, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong

Microelectron. Reliab., 2018

Failure signature analysis of power-opens in DDR3 SDRAMs.

Tan Li, Hosung Lee, GeunYong Bak, Sanghyeon Baeg

Microelectron. Reliab., 2018

Signal characteristic and test exploitation for intermittent nanometer-scale cracks.

Hosung Lee, Sanghyeon Baeg

Microelectron. Reliab., 2018

Study of TID effects on one row hammering using gamma in DDR4 SDRAMs.

Donghyuk Yun, Myungsang Park, Chul Seung Lim, Sanghyeon Baeg

Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017

Resource-Efficient SRAM-Based Ternary Content Addressable Memory.

Ali Ahmed, Kyungbae Park, Sanghyeon Baeg

IEEE Trans. Very Large Scale Integr. Syst., 2017

Temporal and frequency characteristic analysis of margin-related failures caused by an intermittent nano-scale fracture of the solder ball in a BGA package device.

Hosung Lee, Sanghyeon Baeg, Nelson Hua, Shi-Jie Wen

Microelectron. Reliab., 2017

An alternative approach to measure alpha-particle-induced SEU cross-section for flip-chip packaged SRAM devices: High energy alpha backside irradiation.

Saqib A. Khan, Chul Seung Lim, GeunYong Bak, Sanghyeon Baeg, Soonyoung Lee

Microelectron. Reliab., 2017

2016

Statistical distributions of row-hammering induced failures in DDR3 components.

Kyungbae Park, Donghyuk Yun, Sanghyeon Baeg

Microelectron. Reliab., 2016

Experiments and root cause analysis for active-precharge hammering fault in DDR3 SDRAM under 3 × nm technology.

Kyungbae Park, Chul Seung Lim, Donghyuk Yun, Sanghyeon Baeg

Microelectron. Reliab., 2016

Erratum: Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation [IEICE Electronics Express Vol. 13 (2016) No. 17 pp. 20160627].

Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg

IEICE Electron. Express, 2016

Assessing alpha-particle-induced SEU sensitivity of flip-chip bonded SRAM using high energy irradiation.

Saqib A. Khan, Shi-Jie Wen, Sanghyeon Baeg

IEICE Electron. Express, 2016

2015

Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams.

GeunYong Bak, Soonyoung Lee, Hosung Lee, Kyungbae Park, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Charlie Slayman

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory.

Syed Mohsin Abbas, Soonyoung Lee, Sanghyeon Baeg, Sungju Park

IEEE Trans. Computers, 2014

Single Event Resilient Dynamic Logic Designs.

Haibin Wang, Mulong Li, Li Chen, Rui Liu, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong, Rita Fung, Jinshun Bi

J. Electron. Test., 2014

2013

Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.

Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong

Microprocess. Microsystems, 2013

2012

Characterizing the Capacitive Crosstalk in SRAM Cells Using Negative Bit-Line Voltage Stress.

Jongsun Bae, Sanghyeon Baeg, Sungju Park

IEEE Trans. Instrum. Meas., 2012

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory.

Zahid Ullah, Kim Ilgon, Sanghyeon Baeg

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Soft Error Issues with Scaling Technologies.

Sanghyeon Baeg, Jongsun Bae, Soonyoung Lee, Chul Seung Lim, Sang Hoon Jeon, Hyeonwoo Nam

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Mitigating the effects of large multiple cell upsets (MCUs) in memories.

Juan Antonio Maestro, Pedro Reviriego, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong

ACM Trans. Design Autom. Electr. Syst., 2011

Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations.

Changmin Jung, Sanghyeon Baeg, Shi-Jie Wen, Richard Wong

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Designing ad-hoc scrubbing sequences to improve memory reliability against soft errors.

Pedro Reviriego, Juan Antonio Maestro, Sanghyeon Baeg

Proceedings of the 48th Design Automation Conference, 2011

2010

Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals.

Sanghyeon Baeg, Shi-Jie Wen, Richard Wong

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

2009

Null Detector Circuit Design Scheme for Detecting Defective AC-Coupled Capacitors in Differential Signaling.

Sanghyeon Baeg

IEEE Trans. Instrum. Meas., 2009

A di/dt Compensation Technique in Delay Testing by Disconnecting Power Pins.

Sanghyeon Baeg

IEEE Trans. Instrum. Meas., 2009

2008

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line.

Sanghyeon Baeg

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Low Power Configuration Strategy of TCAM Lookup Table.

Sanghyeon Baeg

IEICE Trans. Commun., 2008

2007

Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.

Sanghyeon Baeg

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Efficient Interconnect Test Patterns for Crosstalk and Static Faults.

Pyoungwoo Min, Hyunbean Yi, Jaehoon Song, Sanghyeon Baeg, Sungju Park

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005

Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis.

Sanghyeon Baeg, Sung Soo Chung

IEEE Trans. Very Large Scale Integr. Syst., 2005

2001

AC-JTAG: empowering JTAG beyond testing DC nets.

Sung Soo Chung, Sanghyeon Baeg

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

1999

A cost-effective design for testability: clock line control and test generation using selective clocking.

Sanghyeon Baeg, William A. Rogers

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1994

Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation.

Sanghyeon Baeg, William A. Rogers

Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.

Sanghyeon Baeg, William A. Rogers

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994