Wolfgang Günther

Affiliations:
  • OneSpin Solutions GmbH, Munich, Germany
  • University of Freiburg, Germany (PhD 2001)


According to our database1, Wolfgang Günther authored at least 51 papers between 1998 and 2006.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2006
Orthogonal Hypergraph Drawing for Improved Visibility.
J. Graph Algorithms Appl., 2006

2005
Combining ordered best-first search with branch and bound for exact BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Orthogonal Circuit Visualization Improved by Merging the Placement and Routing Phases.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Some Common Synthesis-Simulation-Mismatches.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Efficient (Non-)Reachability Analysis of Counterexamples.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2004

Orthogonal hypergraph routing for improved visibility.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Minimization of the expected path length in BDDs based on local changes.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
An improved branch and bound algorithm for exact BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams.
IEEE Trans. Computers, 2003

Recursive bi-partitioning of netlists for large number of partitions.
J. Syst. Archit., 2003

Pattern-based verification of connections to intellectual property cores.
Integr., 2003

Cross Reduction for Orthogonal Circuit Visualization.
Proceedings of the International Conference on VLSI, 2003

The Case for 2-POF.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2003

Combination of Lower Bounds in Exact BDD Minimization.
Proceedings of the 2003 Design, 2003

2002
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.
VLSI Design, 2002

Minimization of free BDDs.
Integr., 2002

Minimization of Word-Level Decision Diagrams.
Integr., 2002

Crossing Reduction by Windows Optimization.
Proceedings of the Graph Drawing, 10th International Symposium, 2002

2001
Minimierung von Entscheidungsdiagrammen und Anwendungen im Schaltkreisentwurf.
PhD thesis, 2001

Using lower bounds during dynamic BDD minimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

History-based dynamic BDD minimization.
Integr., 2001

Performance Driven Optimization for MUX based FPGAs.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Implementation of Read- k-times BDDs on Top of Standard BDD Packages.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Efficient Pattern-Based Verification of Connections to Intellectual Property Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2001

Selection of Efficient Re-Ordering Heuristics for MDD Construction.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Level Assignment for Displaying Combinational Logic.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement.
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Efficient Pattern-Based Verification of Connections to IP Cores .
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Application of linearly transformed BDDs in sequential verification.
Proceedings of ASP-DAC 2001, 2001

2000
Fast exact minimization of BDD's.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs.
J. Syst. Archit., 2000

On the computational power of linearly transformed BDDs.
Inf. Process. Lett., 2000

A Method for Approximate Equivalence Checking.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Dynamic Re-Encoding During MDD Minimization.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Lower Bound Sifting for MDDs.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Optimization of sequential verification by history-based dynamic minimization of BDDs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Improving EAs for Sequencing Problems.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints.
Proceedings of the Genetic and Evolutionary Computation Conference (GECCO '00), 2000

<i>k</i>-Layer Straightline Crossing Minimization by Speeding Up Sifting.
Proceedings of the Graph Drawing, 8th International Symposium, 2000

Verification of Designs Containing Black Boxes.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Testability of Circuits Derived from Lattice Diagrams.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000

1999
Creating hard problem instances in logic synthesis using exact minimization.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Minimization of BDDs using linear transformations based on evolutionary techniques.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

History-Based Dynamic Minimization During BDD Construction.
Proceedings of the VLSI: Systems on a Chip, 1999

Efficient manipulation algorithms for linearly transformed BDDs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Efficient Graph Coloring by Evolutionary Algorithms.
Proceedings of the Computational Intelligence, 1999

Generation of Optimal Universal Logic Modules.
Proceedings of the 25th EUROMICRO '99 Conference, 1999

Using Lower Bounds During Dynamic BDD Minimization.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Linear Transformations and Exact Minimization of BDDs.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Fast Exact Minimization of BDDs.
Proceedings of the 35th Conference on Design Automation, 1998


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