Mitchell A. Thornton

According to our database1, Mitchell A. Thornton authored at least 107 papers between 1993 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Keyboard Snooping from Mobile Phone Arrays with Mixed Convolutional and Recurrent Neural Networks.
IMWUT, 2019

Entanglement in Higher-Radix Quantum Systems.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Task Value Calculus: Multi-Objective Trade off Analysis Using Multiple-Valued Decision Diagrams.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

A quantum computational compiler and design tool for technology-specific targets.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018
Higher-Radix Chrestenson Gates for Photonic Quantum Computation.
FLAP, 2018

Multiple-Valued Random Digit Extraction.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

A Radix-4 Chrestenson Gate for Optical Quantum Computation.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017
Automated Markov-chain based analysis for large state spaces.
Proceedings of the 2017 Annual IEEE International Systems Conference, 2017

Quantum Photonic TRNG with Dual Extractor.
Proceedings of the Quantum Technology and Optimization Problems, 2017

2016
QMDDs: Efficient Quantum Function Representation and Manipulation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Fixed-Point Squaring Algorithm Using an Implicit Arbitrary Radix Number System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Reliability block diagram extensions for non-parametric probabilistic analysis.
Proceedings of the Annual IEEE Systems Conference, 2016

Implementation of switching circuit models as transfer functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Demographic Group Prediction Based on Smart Device User Recognition Gestures.
Proceedings of the 15th IEEE International Conference on Machine Learning and Applications, 2016

2015
Simulation and Implication Using a Transfer Function Model for Switching Logic.
IEEE Trans. Computers, 2015

Modeling System Threat Probabilities Using Mixed-Radix Multiple-Valued Logic Decision Diagrams.
Multiple-Valued Logic and Soft Computing, 2015

Quantum Multiple-Valued Decision Diagrams Containing Skipped Variables.
Multiple-Valued Logic and Soft Computing, 2015

Edge Reduction for EVMDDs to Speed Up Analysis of Multi-state Systems.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Demographic Group Classification of Smart Device Users.
Proceedings of the 14th IEEE International Conference on Machine Learning and Applications, 2015

2014
Modeling Digital Switching Circuits with Linear Algebra
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2014

Clock Distribution Area Reduction Using a Multiple-Valued Clocking Approach.
Multiple-Valued Logic and Soft Computing, 2014

On Optimizations of Edge-Valued MDDs for Fast Analysis of Multi-State Systems.
IEICE Transactions, 2014

System Probability Distribution Modeling Using MDDs.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Setting the stage for CE2016: A revised body of knowledge.
Proceedings of the IEEE Frontiers in Education Conference, 2014

2013
Spectral Response of Ternary Logic Netlists.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Ternary Logic Network Justification Using Transfer Matrices.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

A Transfer Function Model for Ternary Switching Logic Circuits.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Embedded and real-time systems classes in traditional and distance education format.
Proceedings of the IEEE Frontiers in Education Conference, 2013

Computer engineering curriculum guidelines.
Proceedings of the IEEE Frontiers in Education Conference, 2013

2012
Reversible Logic Synthesis Based on Decision Diagram Variable Ordering.
Multiple-Valued Logic and Soft Computing, 2012

Professional Licensure for Software Engineers: An Update.
Computing in Science and Engineering, 2012

Computer engineering review task force report.
Proceedings of the 43rd ACM technical symposium on Computer science education, 2012

Global Multiple-Valued Clock Approach for High- Performance Multi-phase Clock Integrated Circuits.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Modeling Medical System Threats with Conditional Probabilities Using Multiple-Valued Logic Decision Diagrams.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Using the Asynchronous Paradigm for Reversible Sequential Circuit Implementation.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Uncle - An RTL Approach to Asynchronous Design.
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2011
Keyboard Dynamics.
Proceedings of the Encyclopedia of Cryptography and Security, 2nd Ed., 2011

Using Multiple-Valued Logic Decision Diagrams to Model System Threat Probabilities.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

On the Skipped Variables of Quantum Multiple-Valued Decision Diagrams.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2010
Digital System Verification: A Combined Formal Methods and Simulation Framework
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2010

To PE or not to PE: the Sequel.
Computing in Science and Engineering, 2010

Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

2009
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures.
IEEE Trans. Computers, 2009

Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics.
Multiple-Valued Logic and Soft Computing, 2009

On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering.
Proceedings of the ISMVL 2009, 2009

Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©.
Proceedings of the ISMVL 2009, 2009

A Low Power High Performance Radix-4 Approximate Squaring Circuit.
Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008
Components of disaster-tolerant computing: analysis of disaster recovery, IT application downtime and executive visibility.
IJBIS, 2008

Quantum Logic Implementation of Unary Arithmetic Operations.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits.
Proceedings of the Design, Automation and Test in Europe, 2008

Multiple Valued Logic - Concepts and Representations.
Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers, ISBN: 978-1-59829-190-2, 2008

2007
Multiple Valued Logic: Concepts and Representations
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2007

QMDD Minimization Using Sifting for Variable Reordering.
Multiple-Valued Logic and Soft Computing, 2007

Variable Reordering and Sifting for QMDD.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Components and Analysis of Disaster Tolerant Computing.
Proceedings of the 26th IEEE International Performance Computing and Communications Conference, 2007

Advances in Quantum Computing Fault Tolerance and Testing.
Proceedings of the Tenth IEEE International Symposium on High Assurance Systems Engineering (HASE 2007), 2007

Automatic High Level Assertion Generation and Synthesis for Embedded System Design.
Proceedings of the Forum on specification and Design Languages, 2007

2006
Introduction to Logic Synthesis using Verilog HDL
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, 2006

QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

A Quantum CAD Accelerator Based on Grover's Algorithm for Finding the Minimum Fixed Polarity Reed-Muller Form.
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

A digit serial algorithm for the integer power operation.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A Decision Diagram Package for Reversible and Quantum Circuit Simulation.
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006

Performance Evaluation of a Novel Direct Table Lookup Method and Architecture with Application to 16-bit Integer Functions.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Early evaluation for performance enhancement in phased logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A Coarse-Grain Phased Logic CPU.
IEEE Trans. Computers, 2005

A Framework and Process for Curricular Integration and Innovation Using Project Based Interdisciplinary Teams.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

Hardware Implementation of an Additive Bit-Serial Algorithm for the Discrete Logarithm Modulo 2k.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

The Karhunen-Loève Transform of Discrete MVL Functions.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

Table Lookup Structures for Multiplicative Inverses Modulo 2k.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs.
Multiple-Valued Logic and Soft Computing, 2004

A Genetic Approach for Conjunction Scheduling in Symbolic Equivalence Checking.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Test vector generation and classification using FSM traversals.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003
Performance Evaluation of a Parallel Decoupled Data Driven Multiprocessor.
Parallel Processing Letters, 2003

A signed binary addition circuit based on an alternative class of addition tables.
Computers & Electrical Engineering, 2003

A Fine-Grain Phased Logic CPU.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Spectral Transforms of Mixed-radix MVL Functions.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.
Proceedings of the 2003 Design, 2003

A Coarse-Grain Phased Logic CPU.
Proceedings of the 9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 2003

2002
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs.
VLSI Design, 2002

On-line Error Detection in a Carry-free Adder.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Low Power Optimization Techniques for BDD Mapped Finite State Machines.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Multi-Output Timed Shannon Circuits.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Efficient Adder Circuits Based on a Conservative Reversible Logic Gate.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Chrestenson Spectrum Computation Using Cayley Color Graphs.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Switching activity estimation of finite state machines for low power synthesis.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Generalized Early Evaluation in Self-Timed Circuits.
Proceedings of the 2002 Design, 2002

2001
Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Spectral decision diagrams using graph transformations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Low power optimization technique for BDD mapped circuits.
Proceedings of ASP-DAC 2001, 2001

Spectral techniques in VLSI CAD.
Kluwer, ISBN: 978-0-7923-7433-6, 2001

2000
Boolean function representation and spectral characterization using AND/OR graphs.
Integration, 2000

Cache Resident Data Locality Analysis.
Proceedings of the MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August, 2000

A Method for Approximate Equivalence Checking.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

MDD-Based Synthesis of Multi-Valued Logic Networks.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Computation of Spectral Information from Logic Netlists.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999
Behavioral synthesis of combinational logic using spectral-based heuristics.
ACM Trans. Design Autom. Electr. Syst., 1999

Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities.
Proceedings of the 1999 Design, 1999

1998
Integration of CAD tools and structured design principles in an undergraduate computer engineering curriculum.
Proceedings of the 1998 workshop on Computer architecture education, 1998

1997
Signed Binary Addition Circuitry with Inherent Even Parity Outputs.
IEEE Trans. Computers, 1997

Graph Analysis and Transformation Techniques for Runtime Minimization in Multi-Threaded Architectures.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

1995
Efficient calculation of spectral coefficients and their applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

1993
An iterative combinational logic synthesis technique using spectral information.
Proceedings of the European Design Automation Conference 1993, 1993


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