Xiaobing Shi

According to our database1, Xiaobing Shi authored at least 8 papers between 2012 and 2017.

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Bibliography

2017
A generic embedded sequence generator for constrained-random validation with weighted distributions.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2016
On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Generating Cyclic-Random Sequences in a Constrained Space for In-System Validation.
IEEE Trans. Computers, 2016

2015
On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon Validation.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2014
On-chip constrained random stimuli generation for post-silicon validation using compact masks.
Proceedings of the 2014 International Test Conference, 2014

An 8Gb/s 0.75mW/Gb/s injection-locked receiver with constant jitter tracking bandwidth and accurate quadrature clock generation in 40nm CMOS.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

On Supporting Sequential Constraints for On-Chip Generation of Post-silicon Validation Stimuli.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2012
A fast-lock-in wide-range harmonic-free all-digital DLL with a complementary delay line.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012


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