Xilong Kang

According to our database, Xilong Kang authored at least 4 papers in 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

KV-Cache Oriented Query-Aware Sparse Attention Accelerator With Cross-Stage Precision-Configurable Digital CIM.

Yang Zhang, Xilong Kang, Weixuan Wang, Yizhi Ding, Lizheng Ren, Yiran Zhang, Ruiqi Tan, Zhen Wang, Hao Cai, Bo Liu

IEEE Trans. Circuits Syst. II Express Briefs, August, 2025

A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network.

Qinfan Wang, Yuan Song, Xilong Kang, Qingwen Wei, Cai Hao, Bo Liu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs.

Bo Liu, Xingyu Xu, Yang Zhang, Xilong Kang, Qingwen Wei, Zihan Zou, Jun Yang, Hao Cai, Xin Si

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device.

Xilong Kang, Qingwen Wei, Ningyuan Li, Xingyu Xu, Hao Cai, Bo Liu

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025