Lizheng Ren

According to our database1, Lizheng Ren authored at least 6 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Learning-driven Physically-aware Large-scale Circuit Gate Sizing.
CoRR, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022
SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU.
IEEE J. Solid State Circuits, 2022

2021
29.8 115nA@3V ULPMark-CP Score 1205 SCVR-Less Dynamic Voltage-Stacking Scheme for IoT MCU.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021


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