Xingyuan Tong

Orcid: 0000-0002-0697-1049

According to our database1, Xingyuan Tong authored at least 38 papers between 2009 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
An 11-bit Nyquist SAR-VCO Hybrid ADC with a Reused Ring-VCO for Power Reduction.
Circuits Syst. Signal Process., March, 2024

2023
A 14-bit 1-MS/s SAR ADC with a segmented capacitor array and background mismatch calibration for IoT sensing applications.
Microelectron. J., November, 2023

Enhancing the Measurement Sensitivity and Repeatability of Electrolyte-Insulator-Semiconductor Capacitor Sensor With Impedance Conversion.
IEEE Trans. Instrum. Meas., 2023

A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023

A 0.6-1.8 V/0.4-1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes.
Circuits Syst. Signal Process., 2023

2022
A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Low-Phase-Error Small-Area 4-Phase DLL With a Single-Ended-Differential-Single-Ended Voltage-Controlled Delay Line.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A 200 Hz-to-10 kHz bandwidth 11.83-ENOB level-crossing ADC with single continuous-time comparator.
Microelectron. J., 2022

A 0.6-V 12-bit 13.2-fJ/conversion-step SAR ADC with time-domain VCDL-based comparator and metastability immunity technique.
Microelectron. J., 2022

A 14-bit 1.2-V low power SAR ADC with digital background calibration in 0.18 μm CMOS.
Microelectron. J., 2022

A 0.6 V Fast-Transient-Response 180 nm CMOS Digital LDO with Coarse-Fine Tuning and Analog Enhancement.
Circuits Syst. Signal Process., 2022

A 0.6-V, 1.56-nW, 5.87-ppm/°C, 0.23%/V CMOS-Only Subthreshold Voltage Reference with the Threshold Voltage Difference.
Circuits Syst. Signal Process., 2022

High Energy Efficiency and Linearity Switching Scheme Without Reset Energy for SAR ADC.
Circuits Syst. Signal Process., 2022

2021
Area- and Energy-Efficient Sub-GHz Impulse Radio UWB Transmitter With Output Amplitude Enhancement for Biomedical Implants.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Using Long-Term Earth Observation Data to Reveal the Factors Contributing to the Early 2020 Desert Locust Upsurge and the Resulting Vegetation Loss.
Remote. Sens., 2021

A chaos-based true random number generator based on OTA sharing and non-flipped folded Bernoulli mapping for high-precision ADC calibration.
Microelectron. J., 2021

A three-stage OTA with hybrid active miller enhanced compensation technique for large to heavy load applications.
Microelectron. J., 2021

A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications.
Circuits Syst. Signal Process., 2021

A 1<sup>st</sup>-order noise shaping SAR ADC with dual-capacitor merge-and-split switching scheme for sensor chip.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

A 10-bit SAR ADC with adaptive VCO-based comparator for sensor chip.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021

2020
A 17.6-nW 35.7-ppm/°C Temperature Coefficient All-SVT-MOSFET Subthreshold Voltage Reference in Standard 0.18-μm N-Well CMOS.
IEEE Access, 2020

2019
An Inductively-Powered Wireless Neural Recording and Stimulation System for Freely-Behaving Animals.
IEEE Trans. Biomed. Circuits Syst., 2019

A 10-Bit 120 kS/s SAR ADC Without Reset Energy for Biomedical Electronics.
Circuits Syst. Signal Process., 2019

2017
Low-Power High-Linearity Switching Procedure for Charge-Redistribution SAR ADC.
Circuits Syst. Signal Process., 2017

A Fully Integrated Fast-Response LDO Voltage Regulator with Adaptive Transient Current Distribution.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A 0.6 V 10 bit 120 kS/s SAR ADC for implantable multichannel neural recording.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A 1 V 10 bit 25 kS/s VCO-based ADC for implantable neural recording.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A sub-GHz UWB data transmitter with enhanced output amplitude for implantable bioelectronics.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Improved Switching Energy Reduction Approach in Low-Power SAR ADC for Bioelectronics.
VLSI Design, 2016

Multichannel Wireless Neural Recording AFE Architectures: Analysis, Modeling, and Tradeoffs.
IEEE Des. Test, 2016

Toward a distributed free-floating wireless implantable neural recording system.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015
Noise Modeling and Analysis of SAR ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2011
Novel hybrid D/A structures for high-resolution SAR ADCs - analysis, modeling and realization.
Microelectron. J., 2011

2010
Quasi Delay-Insensitive High Speed Two-Phase Protocol Asynchronous Wrapper for Network on Chips.
J. Comput. Sci. Technol., 2010

A 12-bit 1MS/s Non-calibrating SAR A/D Converter Based on 90nm CMOS Process.
Proceedings of the 2010 International Conference on Machine Vision and Human-machine Interface, 2010

2009
Low-power Capacitor Arrays for Charge Redistribution SAR A-D Converter in 65nm CMOS.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009

A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process.
Proceedings of the 2009 Pacific-Asia Conference on Circuits, Communications and Systems, 2009


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