Xun Jian

Orcid: 0000-0002-7120-7426

Affiliations:
  • Virginia Tech, Blacksburg, VA, USA
  • University of Illinois at Urbana-Champaign, Champaign, IL, USA (former)


According to our database1, Xun Jian authored at least 20 papers between 2013 and 2023.

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Bibliography

2023
SHADE: Enable Fundamental Cacheability for Distributed Deep Learning Training.
Proceedings of the 21st USENIX Conference on File and Storage Technologies, 2023

2022
Self-Reinforcing Memoization for Cryptography Calculations in Secure Memory Systems.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Eager Memory Cryptography in Caches.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

Translation-optimized Memory Compression for Capacity.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021
Quantifying Server Memory Frequency Margin and Using It to Improve Performance in HPC Systems.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
Forget Failure: Exploiting SRAM Data Remanence for Low-overhead Intermittent Computation.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Nonblocking DRAM Refresh.
IEEE Micro, 2019

Quantifying Memory Underutilization in HPC Systems and Using it to Improve Performance via Architecture Support.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Nonblocking Memory Refresh.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

2017
Common-case optimized memory hierarchy for data centers and HPC systems
PhD thesis, 2017

Understanding and Optimizing Power Consumption in Memory Networks.
Proceedings of the 2017 IEEE International Symposium on High Performance Computer Architecture, 2017

2016
Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

2015
Correction prediction: Reducing error correction latency for on-chip memories.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

2014
ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems.
Proceedings of the International Conference for High Performance Computing, 2014

2013
High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity.
IEEE Comput. Archit. Lett., 2013

Low-power, low-storage-overhead chipkill correct via multi-line error correction.
Proceedings of the International Conference for High Performance Computing, 2013

Analyzing Reliability of Memory Sub-systems with Double-Chipkill Detect/Correct.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Adaptive Reliability Chipkill Correct (ARCC).
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013


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