Vilas Sridharan

Orcid: 0000-0002-2944-2799

According to our database1, Vilas Sridharan authored at least 40 papers between 2005 and 2023.

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Bibliography

2023

A Systematic Study of DDR4 DRAM Faults in the Field.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

A Novel Protection Technique for Embedded Memories with Optimized PPA.
Proceedings of the IEEE International Test Conference, 2022

Reliability, Availability, and Serviceability Challenges for Heterogeneous System Design.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
HBM3 RAS: Enhancing Resilience at Scale.
IEEE Comput. Archit. Lett., 2021

Soteria: Towards Resilient Integrity-Protected and Encrypted Non-Volatile Memories.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2019
Nonblocking DRAM Refresh.
IEEE Micro, 2019

2018
Lessons learned from memory errors observed over the lifetime of Cielo.
Proceedings of the International Conference for High Performance Computing, 2018

Exploring and Optimizing Chipkill-Correct for Persistent Memory Based on High-Density NVRAMs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Nonblocking Memory Refresh.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Reliability-Aware Data Placement for Heterogeneous Memory Architecture.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

Evaluating the Resilience of Parallel Applications.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Physics-Informed Machine Learning for DRAM Error Modeling.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017

Automating DRAM Fault Mitigation By Learning From Experience.
Proceedings of the 47th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2017

Lifetime memory reliability data from the field.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Faults in data prefetchers: Performance degradation and variability.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Reliability and Performance Trade-off Study of Heterogeneous Memories.
Proceedings of the Second International Symposium on Memory Systems, 2016

XED: Exposing On-Die Error Detection Information for Strong Memory Reliability.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016

Improving DRAM Fault Characterization through Machine Learning.
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016

2015
Memory Errors in Modern Systems: The Good, The Bad, and The Ugly.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

2014
A Configurable and Strong RAS Solution for Die-Stacked DRAM Caches.
IEEE Micro, 2014

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Real-world design and evaluation of compiler-managed GPU redundant multithreading.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013
Feng shui of supercomputer memory: positional effects in DRAM and SRAM faults.
Proceedings of the International Conference for High Performance Computing, 2013

Low-power, low-storage-overhead chipkill correct via multi-line error correction.
Proceedings of the International Conference for High Performance Computing, 2013

Analyzing Reliability of Memory Sub-systems with Double-Chipkill Detect/Correct.
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

Resilient die-stacked DRAM caches.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Measuring the performance impact of permanent faults in modern microprocessor architectures.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Assessing the impact of hard faults in performance components of modern microprocessors.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
A study of DRAM failures in the field.
Proceedings of the SC Conference on High Performance Computing Networking, 2012

2010
Using hardware vulnerability factors to enhance AVF analysis.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
Eliminating microarchitectural dependency from Architectural Vulnerability.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

2008
Quantifying software vulnerability.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2006
Reducing Data Cache Susceptibility to Soft Errors.
IEEE Trans. Dependable Secur. Comput., 2006

Vulnerability analysis of L2 cache elements to single event upsets.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Balancing Performance and Reliability in the Memory Hierarchy.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005


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