Xuxu Cheng
Orcid: 0000-0003-1717-0850
According to our database1,
Xuxu Cheng authored at least 18 papers
between 2022 and 2026.
Collaborative distances:
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Bibliography
2026
A 112-Gb/s Single-Ended Receiver Front-End With Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, June, 2026
A 2 × 80 Gb/s Single-Ended TAS-TIS PAM-4 Receiver Front-End With Crosstalk Cancellation and Signal Reutilization in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS.
IEEE J. Solid State Circuits, January, 2026
A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
8.9 A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
2025
A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS.
IEEE J. Solid State Circuits, August, 2025
A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS.
IEEE J. Solid State Circuits, July, 2025
A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS.
IEEE J. Solid State Circuits, January, 2025
A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, September, 2024
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 2×56Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
m-Shaped SSPPs Structure to Low Profile Vertically Polarized Antenna With High Gain to Be Conformal With Vehicle Shell.
IEEE Trans. Veh. Technol., 2022
A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022