Yangyi Zhang
Orcid: 0009-0001-2606-7401Affiliations:
- Southern University of Science and Technology, School of Microelectronics, Shenzhen, China
According to our database1,
Yangyi Zhang authored at least 28 papers
between 2020 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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on orcid.org
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Bibliography
2026
A 112-Gb/s Single-Ended Receiver Front-End With Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, June, 2026
A 2 × 80 Gb/s Single-Ended TAS-TIS PAM-4 Receiver Front-End With Crosstalk Cancellation and Signal Reutilization in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2026
A 128-Gb/s PAM-4 Transmitter With Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28-nm CMOS.
IEEE J. Solid State Circuits, January, 2026
A Monolithic CMOS 28Gb/s PAM-4 Optical Receiver Front-End with Lateral-Enhanced P-Well/N-Well APD for VCSEL-Based Links.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2026
A 72Gb/s/pin Single-Ended Driver-Cooperative Coded PAM3 Transceiver with Asymmetric Data-Dependent Equalization and Bias-Peaking for Chiplets and Memory Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
8.9 A 72Gb/s/pin Single-Ended Simultaneous Bi-Directional Transceiver with C-Peaking Leakage Cancellation and Dual-Loop Hybrid Impedance Calibration for Chiplet Interfaces.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026
A 100-Gb/s Burst-Mode Optical Receiver With 9-Tap Pipelined FFE and Amplitude/Phase Adaptation in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2025
ReHIT: Reconfigurable High-Radix Iterative-Taylor Architecture for Ultraprecise Logarithm/Exponential Functions in FPGA-Based Softmax Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., October, 2025
A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS.
IEEE J. Solid State Circuits, August, 2025
A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS.
IEEE J. Solid State Circuits, July, 2025
36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2025
2024
A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS.
IEEE J. Solid State Circuits, September, 2024
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
Live Demonstration: A Video Denoising Co-processor with Non-local Means Algorithm for FHD 30fps Image Sensor.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
A 43.3 bit/cycle Inflate Accelerator Featuring Static-Dynamic Huffman Decoder with Multiple Checkpoints and Optimized End-Of-Block Control for Hyperscale data.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
Anti-Aliasing and Anti-Color-Artifact Demosaicing for High-Resolution CMOS Image Sensor.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A Pseudo 943 million Frames Per Rate High-Speed Camera with Asynchronous Double-Frame Exposure for Motion Estimation.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
A 139 fps pixel-level pipelined binocular stereo vision accelerator with region-optimized semi-global matching.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020