Yosinori Watanabe

According to our database1, Yosinori Watanabe authored at least 57 papers between 1991 and 2017.

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Bibliography

2017
Hardware/Software Codesign Across Many Cadence Technologies.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2013
Share with care: a quantitative evaluation of sharing approaches in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Clearing the clutter: Unified modeling and verification methodology for system level hardware design.
Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Exploiting area/delay tradeoffs in high-level synthesis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Realistic performance-constrained pipelining in high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Speeding-up heuristic allocation, scheduling and binding with SAT-based abstraction/refinement techniques.
ACM Trans. Design Autom. Electr. Syst., 2010

Incremental high-level synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Runtime deadlock analysis for system level design.
Design Autom. for Emb. Sys., 2009

Examining Important Corner Cases: Verification of Interacting Architectural Components in System Designs.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2008
Schedulability Analysis of Petri Nets Based on Structural Properties.
Fundam. Informaticae, 2008

2006
Functional Model Exploration for Multimedia Applications via Algebraic Operators.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Quasi-Static Scheduling of Concurrent Specifications.
Proceedings of the Embedded Systems Handbook., 2005

Eliminating false positives in crosstalk noise analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Quasi-static scheduling of independent tasks for reactive systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

A BMC-based formulation for the scheduling problem of hardware systems.
Int. J. Softw. Tools Technol. Transf., 2005

A structural approach to quasi-static schedulability analysis of communicating concurrent programs.
Proceedings of the EMSOFT 2005, 2005

A Time Slice Based Scheduler Model for System Level Design.
Proceedings of the 2005 Design, 2005

Simulation based deadlock analysis for system level designs.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Logic of constraints: a quantitative performance and functional constraint formalism.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Quasi-static Scheduling for Concurrent Architectures.
Fundam. Informaticae, 2004

Separation of concerns: overhead in modeling and efficient simulation techniques.
Proceedings of the EMSOFT 2004, 2004

Eliminating False Positives in Crosstalk Noise Analysis.
Proceedings of the 2004 Design, 2004

2003
A BMC-formulation for the scheduling problem in highly constrained hardware Systems.
Electron. Notes Theor. Comput. Sci., 2003

Formal Verification for Embedded System Designs.
Design Autom. for Emb. Sys., 2003

Metropolis: An Integrated Electronic System Design Environment.
Computer, 2003

Verifying LOC based functional and performance constraints.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling.
Proceedings of the 2003 Design, 2003

Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.
Proceedings of the 2003 Design, 2003

Gain-based technology mapping for discrete-size cell libraries.
Proceedings of the 40th Design Automation Conference, 2003

Automatic trace analysis for logic of constraints.
Proceedings of the 40th Design Automation Conference, 2003

Temporofunctional crosstalk noise analysis.
Proceedings of the 40th Design Automation Conference, 2003

Quasi-Static Scheduling for Concurrent Architectures.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Case Studies of Model Checking for Embedded System Designs.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

State Space Compression in History Driven Quasi-Static Scheduling.
Proceedings of the Embedded Software for SoC, 2003

Simulation Trace Verification for Quantitative Constraints.
Proceedings of the Embedded Software for SoC, 2003

2002
Formal verification of embedded system designs at multiple levels of abstraction.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Processes, Interfaces and Platforms. Embedded Software Modeling in Metropolis.
Proceedings of the Embedded Software, Second International Conference, 2002

False Path Elimination in Quasi-Static Scheduling.
Proceedings of the 2002 Design, 2002

Concurrent execution semantics and sequential simulation algorithms for the metropolis meta-model.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Quasi-Static Scheduling of Independent Tasksfor Reactive Systems.
Proceedings of the Applications and Theory of Petri Nets 2002, 2002

Modeling and Designing Heterogeneous Systems.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2001
Constraints specification at higher levels of abstraction.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Generation of minimal size code for scheduling graphs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Area and search space control for technology mapping.
Proceedings of the 37th Conference on Design Automation, 2000

Task generation and compile-time scheduling for mixed data-control embedded software.
Proceedings of the 37th Conference on Design Automation, 2000

1999
Designing digital video systems: modeling and scheduling.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

Quasi-Static Scheduling of Embedded Software Using Equal Conflict Nets.
Proceedings of the Application and Theory of Petri Nets 1999, 1999

1997
Logic decomposition during technology mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

1996
Permissible functions for multioutput components in combinational logic optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

1995
A delay model for logic synthesis of continuously-sized networks.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994
State Minimization of Pseudo Non-Deterministic FSM's.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993
Heuristic minimization of multiple-valued relations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Logic Optimization with Multi-Output Gates.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Heuristic Minimization of Synchronous Relations.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

The maximum set of permissible behaviors for FSM networks.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1991
Incremental Synthesis for Engineering Changes.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Heuristic Minimazation of Multiple-Valued Relations.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991


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