Yana Esteves Krasteva

According to our database1, Yana Esteves Krasteva authored at least 9 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2010
Reconfigurable Networks on Chip: DRNoC architecture.
J. Syst. Archit., 2010

Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Generic Systolic Array for Run-Time Scalable Cores.
Proceedings of the Reconfigurable Computing: Architectures, 2010

2008
A Fast Emulation-Based NoC Prototyping Framework.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

2007
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Partial Reconfiguration for Core Reallocation and Flexible Communications.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Flexible Core Reallocation for Virtex II Structures.
Proceedings of The 2005 International Conference on Engineering of Reconfigurable Systems and Algorithms, 2005


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