Yann Kieffer

Orcid: 0000-0001-5904-0515

According to our database1, Yann Kieffer authored at least 19 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Low-cost Low-Power Implementation of Binary Edwards Curve for Secure Passive RFID Tags.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

2022
Minimizing makespan under data prefetching constraints for embedded vision systems: a study of optimization methods and their performance.
Oper. Res., 2022

2021
Survey: Vulnerability Analysis of Low-Cost ECC-Based RFID Protocols against Wireless and Side-Channel Attacks.
Sensors, 2021

Novel ECC-Based RFID Mutual Authentication Protocol for Emerging IoT Applications.
IEEE Access, 2021

2020
An Experimental Study on Symmetry Breaking Constraints Impact for the One Dimensional Bin-Packing Problem.
Proceedings of the 2020 Federated Conference on Computer Science and Information Systems, 2020

New Symmetry-less ILP Formulation for the Classical One Dimensional Bin-Packing Problem.
Proceedings of the Computing and Combinatorics - 26th International Conference, 2020

2016
Efficient algorithms for memory management in embedded vision systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Formulation and Practical Solution for the Optimization of Memory Accesses in Embedded Vision Systems.
Proceedings of the 2016 Federated Conference on Computer Science and Information Systems, 2016

Memory management in embedded vision systems: Optimization problems and solution methods.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Applying Operations Research to Design for Test Insertion Problems.
Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2013
Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New techniques for selecting test frequencies for linear analog circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Efficient minimization of test frequencies for linear analog circuits.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.
VLSI Design, 2012

2011
A Global Optimization for Scan Chain Insertion at the RT-level.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A multi-objective optimization for memory BIST sharing using a genetic algorithm.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

An Innovative Methodology for Scan Chain Insertion and Analysis at RTL.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
A shared BIST optimization methodology for memory test.
Proceedings of the 15th European Test Symposium, 2010

2003
The facets of the polytope of modules of a graph.
Oper. Res. Lett., 2003


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