Stéphane Mancini

According to our database1, Stéphane Mancini authored at least 30 papers between 1999 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Compression and Speed-up of Convolutional Neural Networks Through Dimensionality Reduction for Efficient Inference on Embedded Multiprocessor.
J. Signal Process. Syst., 2022

Efficient Implementation of Convolution and Winograd on ASMP Embedded Multicore Vector Processor.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020

Tunable CNN Compression Through Dimensionality Reduction.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

Speeding-up CNN inference through dimensionality reduction.
Proceedings of the 2019 Conference on Design and Architectures for Signal and Image Processing, 2019

Efficient algorithms for memory management in embedded vision systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Prototyping a Panoptic Camera by means of High Level Synthesis: Demo.
Proceedings of the 10th International Conference on Distributed Smart Camera, 2016

Formulation and Practical Solution for the Optimization of Memory Accesses in Embedded Vision Systems.
Proceedings of the 2016 Federated Conference on Computer Science and Information Systems, 2016

Memory management in embedded vision systems: Optimization problems and solution methods.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Estimating the Potential Speedup of Computer Vision Applications on Embedded Multiprocessors.
CoRR, 2015

Image tiling for embedded applications with non-linear constraints.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015

Fast parallel application and multiprocessor design space exploration from sequential code.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.
J. Electronic Imaging, 2014

Application-level Performance Optimization: A Computer Vision Case Study on STHORM.
Proceedings of the International Conference on Computational Science, 2014

Closed-loop adaptive and stochastic prefetch mechanism for data array.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Design of a pseudo-log image transform IP in an HLS-based memory management framework.
Proceedings of the Real-Time Image and Video Processing 2013, 2013

Exploration of 3D grid caching strategies for ray-shooting.
J. Real Time Image Process., 2012

Enhancing non-linear kernels by an optimized memory hierarchy in a High Level Synthesis flow.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Effficient stackless ray traversal for bounding sphere hierarchies with CUDA.
Proceedings of the International Conference on Computational Science, 2010

Calibrating a predictive cache emulator for SoC design.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

Efficient Data Access Management for FPGA-Based Image Processing SoCs.
Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Another take on functional system-level design and modeling.
Proceedings of the Forum on specification and Design Languages, 2009

High Efficiency Reconfigurable Cache for Image Processing.
Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

High Speed 3D Tomography on CPU, GPU, and FPGA.
EURASIP J. Embed. Syst., 2008

Simulation results of a small animal liquid xenon PET detector.
Proceedings of the 2008 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2008

Automatic generation of a parallel tile processing unit for algorithms with non-affine array references.
Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, 2008

Hardware/software 2D-3D backprojection on a SoPC platform.
Proceedings of the 2006 ACM Symposium on Applied Computing (SAC), 2006

Ray Casting on a SOPC : Algorithm and Memory Hierarchy Trade-Off.
Proceedings of the Sixth International Conference on Computer and Information Technology (CIT 2006), 2006

Cued speech hand gestures recognition tool.
Proceedings of the 13th European Signal Processing Conference, 2005

LUX: A Heterogeneous Parallel Computer Dedicated to Ray Tracing.
Scalable Comput. Pract. Exp., 2000

LUX: An Heterogeneous Function Composition Parallel Computer for Graphics.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999