Salvador Mir

Orcid: 0000-0001-9911-8946

According to our database1, Salvador Mir authored at least 135 papers between 1994 and 2023.

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Bibliography

2023
Noise modeling using look-up tables and DC measurements for cryogenic applications.
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Special Session: A high-frequency sinusoidal signal generation using harmonic cancellation.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023

A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022


On-chip calibration for high-speed harmonic cancellation-based sinusoidal signal generators.
Proceedings of the IEEE 31st Asian Test Symposium, 2022

2021
Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators based on harmonic cancellation.
Proceedings of the 26th IEEE European Test Symposium, 2021

2020
Estimation of Analog/RF Parametric Test Metrics Based on a Multivariate Extreme Value Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Static linearity BIST for V<sub>cm</sub>-based switching SAR ADCs using a reduced-code measurement technique.
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

On-chip reduced-code static linearity test of V<sub>cm</sub>-based switching SAR ADCs using an incremental analog-to-digital converter.
Proceedings of the IEEE European Test Symposium, 2020

2019
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Reduced-Code Techniques for On-Chip Static Linearity Test of SAR ADCs.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

Efficient generation of data sets for one-shot statistical calibration of RF/mm-wave circuits.
Proceedings of the 16th International Conference on Synthesis, 2019

Yield Recovery of mm-Wave Power Amplifiers using Variable Decoupling Cells and One-Shot Statistical Calibration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 52 dB-SFDR 166 MHz sinusoidal signal generator for mixed-signal BIST applications in 28 nm FDSOI technology.
Proceedings of the 24th IEEE European Test Symposium, 2019

On the use of causal feature selection in the context of machine-learning indirect test.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Practical Harmonic Cancellation Techniques for the On-Chip Implementation of Sinusoidal Signal Generators for Mixed-Signal BIST Applications.
J. Electron. Test., 2018

Reduced-code static linearity test of SAR ADCs using a built-in incremental ∑Δ converter.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Assisted test design for non-intrusive machine learning indirect test of millimeter-wave circuits.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2017
Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

Mixed-signal BIST computation offloading using IEEE 1687.
Proceedings of the 22nd IEEE European Test Symposium, 2017

Design of a sinusoidal signal generator with calibrated harmonic cancellation for mixed-signal BIST in a 28 nm FDSOI technology.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΣΔ ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs.
J. Electron. Test., 2016

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques.
IEEE Des. Test, 2016

Linearity test of high-speed high-performance ADCs using a self-testable on-chip generator.
Proceedings of the 21th IEEE European Test Symposium, 2016

ADC Techniques for Optimized Conversion Time in CMOS Image Sensors.
Proceedings of the Image Sensors and Imaging Systems 2016, 2016

Built-in test of millimeter-Wave circuits based on non-intrusive sensors.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A Tool for Analog/RF BIST Evaluation Using Statistical Models of Circuit Parameters.
ACM Trans. Design Autom. Electr. Syst., 2015

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors.
J. Electron. Test., 2015

Horizontal-FPN fault coverage improvement in production test of CMOS imagers.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times.
Proceedings of the 2015 IEEE International Test Conference, 2015

Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

High frequency jitter estimator for SoCs.
Proceedings of the 20th IEEE European Test Symposium, 2015

2014
Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST.
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Review of temperature sensors as monitors for RF-MMW built-in testing and self-calibration schemes.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Solutions for the self-adaptation of communicating systems in operation.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Low-cost EVM built-in test of RF transceivers.
Proceedings of the 9th International Design and Test Symposium, 2014

On-Chip Implementation of an Integrator-Based Servo-Loop for ADC Static Linearity Test.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Reduced-Code Linearity Testing of Pipeline ADCs.
IEEE Des. Test, 2013

Reduced code linearity testing of pipeline adcs in the presence of noise.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Defect-oriented non-intrusive RF test using on-chip temperature sensors.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Minimizing Test Frequencies for Linear Analog Circuits: New Models and Efficient Solution Methods.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

New techniques for selecting test frequencies for linear analog circuits.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

BIST of interconnection lines in the pixel matrix of CMOS imagers.
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

Fault modeling and diagnosis for nanometric analog circuits.
Proceedings of the 2013 IEEE International Test Conference, 2013

True non-intrusive sensors for RF built-in test.
Proceedings of the 2013 IEEE International Test Conference, 2013

Efficient minimization of test frequencies for linear analog circuits.
Proceedings of the 18th IEEE European Test Symposium, 2013

Multivariate statistical techniques for analog parametric test metrics estimation.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

Statistical modelling of analog circuits for test metrics computation.
Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

2012
Diagnosis of Local Spot Defects in Analog Circuits.
IEEE Trans. Instrum. Meas., 2012

Adaptive Alternate Analog Test.
IEEE Des. Test Comput., 2012

Analog/RF test ordering in the early stages of production testing.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Experiences with non-intrusive sensors for RF built-in test.
Proceedings of the 2012 IEEE International Test Conference, 2012

Accurate estimation of analog test metrics with extreme circuits.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs.
Proceedings of the 17th IEEE European Test Symposium, 2012

Testing RF circuits with true non-intrusive built-in sensors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Estimation of Analog Parametric Test Metrics Using Copulas.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

RF Front-End Test Using Built-in Sensors.
IEEE Des. Test Comput., 2011

Implicit test of high-speed analog circuits using non-intrusive sensors.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Design of a SAW-based chemical sensor with its microelectronics front-end interface.
Microelectron. J., 2010

Density estimation for analog/RF test problem solving.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Ordering of analog specification tests based on parametric defect level estimation.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Adaptive Logical Control of RF LNA Performances for Efficient Energy Consumption.
Proceedings of the VLSI-SoC: Forward-Looking Trends in IC and Systems Design, 2010

Analog test metrics estimates with PPM accuracy.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Sensors for built-in alternate RF test.
Proceedings of the 15th European Test Symposium, 2010

Low Frequency Test for RF MEMS Switches.
Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Fault diagnosis of analog circuits based on machine learning.
Proceedings of the Design, Automation and Test in Europe, 2010

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Evaluation of Analog/RF Test Measurements at the Design Stage.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Pseudorandom BIST for test and characterization of linear and nonlinear MEMS.
Microelectron. J., 2009

Experimental Validation of a BIST Techcnique for CMOS Active Pixel Sensors.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Parameter identification of RF transceiver blocks using regressive models.
Proceedings of the 9th IFAC Workshop on Programmable Devices and Embedded Systems, 2009

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study.
Proceedings of the 27th International Conference on Computer Design, 2009

Defect Filter for Alternate RF Test.
Proceedings of the 14th IEEE European Test Symposium, 2009

Enrichment of limited training sets in machine-learning-based analog/RF test.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Using Signal Envelope Detection for Online and Offline RF MEMS Switch Testing.
VLSI Design, 2008

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Estimation of Test Metrics for the Optimisation of Analogue Circuit Testing.
J. Electron. Test., 2007

A stereo audio Σ∑ ADC architecture with embedded SNDR self-test.
Proceedings of the 2007 IEEE International Test Conference, 2007

Envelope Detection Based Transition Time Supervision for Online Testing of RF MEMS Switches.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Evaluation of a BIST Technique for CMOS Imagers.
Proceedings of the 16th Asian Test Symposium, 2007

Test Education in the Global Economy.
Proceedings of the 16th Asian Test Symposium, 2007

2006
Built-in-self-test techniques for MEMS.
Microelectron. J., 2006

A BIST Scheme for SNDR Testing of SigmaDelta ADCs Using Sine-Wave Fitting.
J. Electron. Test., 2006

Guest Editorial.
J. Electron. Test., 2006

A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Study of a BIST Technique for CMOS Active Pixel Sensors.
Proceedings of the IFIP VLSI-SoC 2006, 2006

CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Pseudorandom functional BIST for linear and nonlinear MEMS.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
A low-cost digital frequency testing approach for mixed-signal devices using SigmaDelta modulation.
Microelectron. J., 2005

Analog and mixed signal test techniques for SOC development.
Microelectron. J., 2005

On-Chip Pseudorandom MEMS Testing.
J. Electron. Test., 2005

On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Evaluation of impulse response-based BIST techniques for MEMS in the presence of weak nonlinearities.
Proceedings of the 10th European Test Symposium, 2005

A built-in I<sub>DDQ</sub> testing circuit.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach.
Proceedings of the 2005 Design, 2005

2004
On-chip testing of embedded transducers.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

On-chip testing of embedded silicon transducers.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Mems built-in-self-test using MLS.
Proceedings of the 9th European Test Symposium, 2004

A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns.
Proceedings of the 2004 Design, 2004

2003
Building an analogue fault simulation tool and its application to MEMS.
Microelectron. J., 2003

On-Line Testable Decimation Filter Design for AMS Systems.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

An implementation of memory-based on-chip analogue test signal generation.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001
Generation of Electrically Induced Stimuli for MEMS Self-Test.
J. Electron. Test., 2001

Electrically Induced Stimuli For MEMS Self-Test.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

An Analog-based Approach for MEMS Testing.
Proceedings of the 2nd Latin American Test Workshop, 2001

2000
Design of self-checking fully differential circuits and boards.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Extending Fault-Based Testing to Microelectromechanical Systems.
J. Electron. Test., 2000

Towards design and validation of mixed-technology SOCs.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999
On the Integration of Design and Test for Chips Embedding MEMS.
IEEE Des. Test Comput., 1999

Design and Test of MEMs.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Fault modeling of suspended thermal MEMS.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing.
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998

Failure mechanisms and fault classes for CMOS-compatible microelectromechanical systems.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems.
Proceedings of the 1998 Design, 1998

1997
SWITTEST: Automatic Switch-Level Fault Simulation and Test Evaluation of Switched-Capacitor Systems.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Unified built-in self-test for fully differential analog circuits.
J. Electron. Test., 1996

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.
J. Electron. Test., 1996

Design of high-performance band-pass sigma-delta modulator with concurrent error detection.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

ABILBO: Analog BuILt-in Block Observer.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Automatic Test Generation for Maximal Diagnosis of Linear Analogue Circuits.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Analog checkers with absolute and relative tolerances.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Mixed-signal circuits and boards for high safety applications.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
Built-in self-test and fault diagnosis of fully differential analogue circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Re-engineering hardware specifications by exploiting design semantics.
Proceedings of the Proceedings EURO-DAC'94, 1994


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