Yaoru Hou

According to our database, Yaoru Hou authored at least 5 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 40nm 4Mb High-Reliability STT-MRAM Achieving 18ns Write-Time and 94.9% Wafer-Level-Die-Yield Across -55°C-to-125°C.

Yaoru Hou, Haoran Du, Jiongzhe Su, Yibo Liu, Zhenghan Fang, Jia-Le Cui, Shuyu Wang, Chenxing Liu-Sun, Xuezhao Wu, Zhihua Xiao, Bo Liu, Xin Si, Jun Yang, Qiming Shao, Hao Cai

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

AmPEC: Approximate MRAM with Partial Error Correction for Fine-grained Energy-quality Trade-off.

Lan-yang Sun, Yaoru Hou, Hao Cai

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2023

Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.

Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu, Lirida Alves de Barros Naviner

IEEE Des. Test, June, 2023

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.

Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2021

Cryogenic In-MRAM Computing.

Yaoru Hou, We Ge, Yanan Guo, Lirida A. B. Naviner, You Wang, Bo Liu, Jun Yang, Hao Cai

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021