Yassine Hariri

According to our database, Yassine Hariri authored at least 6 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2023

BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU.

Mohammadhossein Askarihemmat, Sean Wagner, Olexa Bilaniuk, Yassine Hariri, Yvon Savaria, Jean-Pierre David

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2013

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.

Claude Thibeault, Yassine Hariri, Syed Rafay Hasan, Christelle Hobeika, Yvon Savaria, Yves Audet, Fatima Zahra Tazi

J. Electron. Test., 2013

2012

Tester Memory Requirements and Test Application Time Reduction for Delay Faults with Digital Captureless Test Sensors.

Claude Thibeault, Yassine Hariri, Christelle Hobeika

J. Electron. Test., 2012

2011

CDelta IDDQ : Improving Current-Based Testing and Diagnosis Through Modified Test Pattern Generation.

Claude Thibeault, Yassine Hariri

IEEE Trans. Very Large Scale Integr. Syst., 2011

2007

Bridging fault diagnostic tool based on DIDDQ probabilistic signatures, circuit layout parasitics and logic errors.

Yassine Hariri, Claude Thibeault

IET Comput. Digit. Tech., 2007

2003

3DSDM: A 3 Data-Source Diagnostic Method.

Yassine Hariri, Claude Thibeault

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003