Shinichi Miyatake

According to our database1, Shinichi Miyatake authored at least 3 papers between 2001 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2005
1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual-clock input-latch scheme and hybrid multi-oxide output buffer.
IEEE J. Solid State Circuits, 2005

2003
A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer.
IEEE J. Solid State Circuits, 2003

2001
A multigigabit DRAM technology with 6F<sup>2</sup> open-bitline cell, distributed overdriven sensing, and stacked-flash fuse.
IEEE J. Solid State Circuits, 2001


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