Ye-Jyun Lin

According to our database, Ye-Jyun Lin authored at least 5 papers between 2010 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.

Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang

ACM Trans. Design Autom. Electr. Syst., 2017

2015

System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach.

Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Tay-Jyi Lin, Chih-Wen Hsueh, Naehyuck Chang

ACM Trans. Embed. Comput. Syst., 2015

A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.

Ye-Jyun Lin, Chia-Lin Yang, Hsiang-Pang Li, Cheng-Yuan Michael Wang

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

2012

Memory access aware power gating for MPSoCs.

Ye-Jyun Lin, Chia-Lin Yang, Jiao-Wei Huang, Naehyuck Chang

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2010

Hierarchical memory scheduling for multimedia MPSoCs.

Ye-Jyun Lin, Chia-Lin Yang, Tay-Jyi Lin, Jiao-Wei Huang, Naehyuck Chang

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010