Hsiang-Pang Li

According to our database¹, Hsiang-Pang Li authored at least 29 papers between 2013 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2023

A digital 3D TCAM accelerator for the inference phase of Random Forest.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2022

Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Non-Volatile Memory Systems and Applications Symposium, 2022

ICE: An Intelligent Cognition Engine with 3D NAND-based In-Memory Computing for Vector Similarity Search Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019

Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks.

[BibT_eX]

[DOI]

Proceedings of the 46th International Symposium on Computer Architecture, 2019

2018

A partnership-based approach to minimize the maximal response time of flash-memory storage systems.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

2017

A Hybrid DRAM/PCM Buffer Cache Architecture for Smartphones with QoS Consideration.

[BibT_eX]

[DOI]

Ye-Jyun Lin

Chia-Lin Yang

Hsiang-Pang Li

Cheng-Yuan Michael Wang

ACM Trans. Design Autom. Electr. Syst., 2017

A Resistance Drift Compensation Scheme to Reduce MLC PCM Raw BER by Over 100× for Storage Class Memory Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2017

Re-Polarization Processing in Extended Polar Codes.

[BibT_eX]

[DOI]

Yu-Ming Huang

Hsie-Chia Chang

Hsiang-Pang Li

IEICE Trans. Commun., 2017

2016

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Disturbance Relaxation for 3D Flash Memory.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Pattern-aware write-back strategy to minimize energy consumption of PCM-based storage systems.

[BibT_eX]

[DOI]

Proceedings of the 5th Non-Volatile Memory Systems and Applications Symposium, 2016

7.3 A resistance-drift compensation scheme to reduce MLC PCM raw BER by over 100× for storage-class memory applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Realizing erase-free SLC flash memory with rewritable programming design.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

A disturbance-aware sub-block design to improve reliability of 3D MLC flash memory.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015

Marching-Based Wear-Leveling for PCM-Based Storage Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

A buffer cache architecture for smartphones with hybrid DRAM/PCM memory.

[BibT_eX]

[DOI]

Ye-Jyun Lin

Chia-Lin Yang

Hsiang-Pang Li

Cheng-Yuan Michael Wang

Proceedings of the IEEE Non-Volatile Memory System and Applications Symposium, 2015

Fine-grained write scheduling for PCM performance improvement under write power budget.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

On Relaxing Page Program Disturbance over 3D MLC Flash Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

A Light-Weighted Software-Controlled Cache for PCM-based Main Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Achieving SLC performance with MLC flash memory.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

How to improve the space utilization of dedup-based PCM storage devices?

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014

EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On Trading Wear-leveling with Heal-leveling.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

A PCM translation layer for integrated memory and storage management.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine.

[BibT_eX]

[DOI]

Kin-Chu Ho

Po-Chao Fang

Hsiang-Pang Li

Cheng-Yuan Michael Wang

Hsie-Chia Chang

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A disturb-alleviation scheme for 3D flash memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Hsiang-Pang Li

Timeline

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On csauthors.net:

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