Yen-Jen Chang

Shih-Hsiang Chen

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

2021

Data Retention-Based Low Leakage Power TCAM for Network Packet Routing.

[BibT_eX]

[DOI]

Kun-Lin Tsai

Yu-Cheng Cheng

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Accuracy-Configurable Radix-4 Adder With a Dynamic Output Modification Scheme.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Low-power ternary content-addressable memory design based on a voltage self-controlled fin field-effect transistor segment.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2020

A Low Power Radix-4 Booth Multiplier With Pre-Encoded Mechanism.

[BibT_eX]

[DOI]

IEEE Access, 2020

2019

Imprecise 4-2 compressor design used in image processing applications.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

2017

Radix-4 adder design with refined carry.

[BibT_eX]

[DOI]

Proceedings of the IEEE Conference on Dependable and Secure Computing, 2017

2016

Low leakage mask vertical control TCAM for network router.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Master-Slave Match Line Design for Low-Power Content-Addressable Memory.

[BibT_eX]

[DOI]

Tung-Chi Wu

IEEE Trans. Very Large Scale Integr. Syst., 2015

2014

Automatic Charge Balancing Content Addressable Memory With Self-control Mechanism.

[BibT_eX]

[DOI]

Kun-Lin Tsai

Yu-Cheng Cheng

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

Improving the performance of port range check for network packet filtering.

[BibT_eX]

[DOI]

Hsiang-Yu Lu

ACM Trans. Design Autom. Electr. Syst., 2013

Low Leakage TCAM for IP Lookup Using Two-Side Self-Gating.

[BibT_eX]

[DOI]

Kun-Lin Tsai

Hsiang-Jen Tsai

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Low-power content-addressable memory design using a double match-line (DML) architecture.

[BibT_eX]

[DOI]

Ya-Chun Lin

Tung-Chi Wu

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

2011

Fast color-spatial feature based image retrieval methods.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2011

A low-power TCAM design using mask-aware match-line (MAML) technique.

[BibT_eX]

[DOI]

Tung-Chi Wu

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Don't-Care Gating (DCG) TCAM Design Used in Network Routing Table.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Using the Dynamic Power Source Technique to Reduce TCAM Leakage Power.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

2009

A High-Performance and Energy-Efficient TCAM Design for IP-Address Lookup.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2009

Low Power Selected Gating Frame Buffer (SGFB) Design.

[BibT_eX]

Jin-Wei Yang

Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

A Novel High Performance Ternary CAM (TCAM) for LPM.

[BibT_eX]

Yung-Feng Cheng

Proceedings of the 2009 International Conference on Embedded Systems & Applications, 2009

2008

Hybrid-Type CAM Design for Both Power and Performance Efficiency.

[BibT_eX]

[DOI]

Yuan-Hong Liao

IEEE Trans. Very Large Scale Integr. Syst., 2008

Exploiting frequent opcode locality for power efficient instruction cache.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Two New Techniques Integrated for Energy-Efficient TLB Design.

[BibT_eX]

[DOI]

Maofeng Lan

IEEE Trans. Very Large Scale Integr. Syst., 2007

Improve CAM power efficiency using decoupled match line scheme.

[BibT_eX]

[DOI]

Yuan-Hong Liao

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

An Energy-Efficient BTB Lookup Scheme for Embedded Processors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

An Alternative Real-Time Filter Scheme to Block Buffering.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

An ultra low-power TLB design.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Lazy BTB: reduce BTB energy consumption using dynamic profiling.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories.

[BibT_eX]

[DOI]

IEEE Micro, 2005

2004

Zero-aware asymmetric SRAM cell for reducing cache power in writing zero.

[BibT_eX]

[DOI]

Chia-Lin Yang

IEEE Trans. Very Large Scale Integr. Syst., 2004

Enhanced object management for high performance web proxies.

[BibT_eX]

[DOI]

Yung-Ching Weng

Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004

Value-Conscious Cache: Simple Technique for Reducing Cache Access Power.

[BibT_eX]

[DOI]

Chia-Lin Yang

Proceedings of the 2004 Design, 2004

2003

Design and analysis of low-power cache using two-level filter scheme.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A power-aware SWDR cell for reducing cache write power.

[BibT_eX]

[DOI]

Chia-Lin Yang

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

2002

ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

An Efficient Two-Level Filter Scheme for Low Power Cache.

[BibT_eX]

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Cache Design for Eliminating the Address Translation Bottleneck and Reducing the Tag Area Cost.

[BibT_eX]

[DOI]

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Energy analysis of bipartition architecture for pipelined circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

Paged cache: an efficient partition architecture for reducing power, area and access time.

[BibT_eX]

[DOI]