Chia-Lin Ho

According to our database, Chia-Lin Ho authored at least 6 papers between 2002 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

New product identification and design through super-system trimming.

D. Daniel Sheu, Jealousy Hong, Chia-Lin Ho

Comput. Ind. Eng., 2017

2016

A 2.6mm² 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications.

Chi-Cheng Ju, Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Hue-Min Lin, Chun-Chia Chen, Min-Hao Chiu, Ping Chao, Ming-Long Wu, Meng-Jye Hu, Sheng-Jen Wang, Che-Hong Chen, Shun-Hsiang Chuang, Hsiu-Yi Lin, Fu-Chun Yeh, Chia-Hung Kao, Yi-Chang Chen, Chia-Lin Ho, Yenchieh Huang, Hsiao-En Chen, Chih-Wen Yang, Hsuan-Wen Peng

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2015

Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems.

Tsu-Ming Liu, Yung-Chang Chang, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Fu-Chun Yeh, Shun-Hsiang Chuang, Hsiu-Yi Lin, Ming-Long Wu, Che-Hong Chen, Chia-Lin Ho, Chi-Cheng Ju

Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015

2003

A novel approach for digital waveform compression.

Edwin Naroska, Shanq-Jang Ruan, Chia-Lin Ho, Said Mchaalia, Feipei Lai, Uwe Schwiegelshohn

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits.

Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Energy analysis of bipartition architecture for pipelined circuits.

Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Chia-Lin Ho, Feipei Lai

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002