Yeu-Horng Shiau

According to our database1, Yeu-Horng Shiau authored at least 17 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

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Bibliography

2019
VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications.
IEEE Trans. Circuits Syst. Video Techn., 2019

FPGA logic design method based on multi resolution image real time acquisition system.
Evolutionary Intelligence, 2019

2018
Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2015
A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications.
IEEE Trans. Intelligent Transportation Systems, 2015

A Weighted Edge-Preserving Smooth Filter for High Dynamic Range Image Display.
J. Inf. Sci. Eng., 2015

2014
Hardware and Software Co-design of the Moving Object Tracking System.
Proceedings of the 2014 Tenth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, 2014

2013
Hardware Implementation of a Fast and Efficient Haze Removal Method.
IEEE Trans. Circuits Syst. Video Techn., 2013

2012
Power-efficient decoder implementation based on state transparent convolutional codes.
IET Circuits, Devices & Systems, 2012

High Dynamic Range Image Rendering with Order-Statistics Filter.
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012

2011
Low Complexity Underwater Image Enhancement Based on Dark Channel Prior.
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

2009
A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images.
IEEE Trans. on Circuits and Systems, 2009

2004
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme.
IEICE Transactions, 2004

2002
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst., 2002

2001
Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1999
A New Pipelined Architecture for Fuzzy Color Correction.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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