Pei-Yin Chen

According to our database1, Pei-Yin Chen authored at least 76 papers between 1999 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A Novel Comparison-Free 1-D Median Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Spatiotemporal Content-Based CU Size Decision Algorithm for HEVC.
IEEE Trans. Broadcast., 2020

High-Efficient Low-Cost VLSI Implementation for Canny Edge Detection.
J. Inf. Sci. Eng., 2020

A Low-Cost VLSI Architecture of the Bilateral Filter for Real-Time Image Denoising.
IEEE Access, 2020

2019
VLSI Design of an Efficient Flicker-Free Video Defogging Method for Real-Time Applications.
IEEE Trans. Circuits Syst. Video Technol., 2019

Clouds Classification from Sentinel-2 Imagery with Deep Residual Learning and Semantic Image Segmentation.
Remote. Sens., 2019

A Hybrid Autoencoder Network for Unsupervised Image Clustering.
Algorithms, 2019

VLSI Implementation for an Adaptive Haze Removal Method.
IEEE Access, 2019

A Low-Cost Design of 2D Median Filter.
IEEE Access, 2019

Baby Care System Design for Multi-Sensor Applications.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

Dual Path Binary Neural Network.
Proceedings of the 2019 International SoC Design Conference, 2019

Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018
Local Binary Pattern Circuit Generator With Adjustable Parameters for Feature Extraction.
IEEE Trans. Intell. Transp. Syst., 2018

Efficient VLSI Architecture for Edge-Oriented Demosaicking.
IEEE Trans. Circuits Syst. Video Technol., 2018

Hardware Design of an Energy-Efficient High-Throughput Median Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Modular Design of High-Efficiency Hardware Median Filter Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

On-chip real-time feature extraction using semantic annotations for object recognition.
J. Real Time Image Process., 2018

Hardware Implementation of an Image Interpolation Method with Controllable Sharpness.
J. Inf. Sci. Eng., 2018

Live Demonstration: Hardware Design of Video Defogging Method for Real-Time Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Deep Residual Neural Network Design for Super-Resolution Imaging.
Proceedings of the New Trends in Computer Technologies and Applications, 2018

2017
Hardware Design of Low-Power High-Throughput Sorting Unit.
IEEE Trans. Computers, 2017

Hardware Implementation of Local Mean Decomposition.
J. Inf. Sci. Eng., 2017

Smart Cage Implementation with Dependable Safety Agent for Dogs.
Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

A Low-Complexity Intra-Field Restoring Method for Interlaced Image.
Proceedings of the International Conference on Video and Image Processing, 2017

2016
Hardware Design and Implementation for Empirical Mode Decomposition.
IEEE Trans. Ind. Electron., 2016

Real-Time Digital Hardware Simulation of the Rodless Pneumatic System.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

An Efficient Quadtree-Based Block Truncation Coding for Digital Image Compression.
Proceedings of the 30th International Conference on Advanced Information Networking and Applications Workshops, 2016

2015
A Study on Energy Saving and CO<sub>2</sub> Emission Reduction on Signal Countdown Extension by Vehicular Ad Hoc Networks.
IEEE Trans. Veh. Technol., 2015

A Low-Cost Hardware Architecture for Illumination Adjustment in Real-Time Applications.
IEEE Trans. Intell. Transp. Syst., 2015

A Low-Power Architecture for the Design of a One-Dimensional Median Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A Weighted Edge-Preserving Smooth Filter for High Dynamic Range Image Display.
J. Inf. Sci. Eng., 2015

2014
An Efficient Hardware Implementation of HOG Feature Extraction for Human Detection.
IEEE Trans. Intell. Transp. Syst., 2014

2013
Hardware Implementation of a Fast and Efficient Haze Removal Method.
IEEE Trans. Circuits Syst. Video Technol., 2013

Design of an Area-Efficient One-Dimensional Median Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

An Efficient Denoising Architecture for Removal of Impulse Noise in Images.
IEEE Trans. Computers, 2013

A Practical Survey of Evaporative Cooling System for Orchids Greenhouse.
Proceedings of the Second International Conference on Robot, Vision and Signal Processing, 2013

Mobile Nursery Construction with Alignment of Sensors for Orchids Breeding.
Proceedings of the Second International Conference on Robot, Vision and Signal Processing, 2013

2012
A Novel Interpolation Chip for Real-Time Multimedia Applications.
IEEE Trans. Circuits Syst. Video Technol., 2012

Power-efficient decoder implementation based on state transparent convolutional codes.
IET Circuits Devices Syst., 2012

Decision-tree based green driving suggestion system for carbon emission reduction.
Proceedings of the 12th International Conference on ITS Telecommunications, 2012

High Dynamic Range Image Rendering with Order-Statistics Filter.
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012

A Low-Complexity Scaling Scheme for Barrel Distortion Correction.
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012

A Dynamic Routing Scheme to Support Reliable TCP Connections on Wireless Mesh Networks.
Proceedings of the 2012 Sixth International Conference on Genetic and Evolutionary Computing, 2012

2011
A Low-Cost VLSI Architecture for Robust Distributed Estimation in Wireless Sensor Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Low Complexity Underwater Image Enhancement Based on Dark Channel Prior.
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

An Efficient Denoising Approach for Random-Valued Impulse Noise in Digital Images.
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

Cyclic Prefix Optimization for OFDM Transmission over Fading Propagation with Bit-Rate and BER Constraints.
Proceedings of the Second International Conference on Innovations in Bio-inspired Computing and Applications, 2011

2010
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Low-Cost VLSI Architecture for Fault-Tolerant Fusion Center in Wireless Sensor Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010

A low-power IP design of Viterbi decoder with dynamic threshold setting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An efficient denoising chip for the removal of impulse noise.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
VLSI Implementation of an Edge-Oriented Image Scaling Processor.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A Collaborative sensor-fault detection scheme for robust distributed estimation in sensor networks.
IEEE Trans. Commun., 2009

A VLSI Implementation of Barrel Distortion Correction for Wide-Angle Camera Images.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A Hybrid Image Restoring Algorithm for Interlaced Video.
IEEE Signal Process. Lett., 2009

2008
An Efficient Design of Variable Length Decoder for MPEG-1/2/4.
IEEE Trans. Multim., 2008

Hardware Implementation for a Genetic Algorithm.
IEEE Trans. Instrum. Meas., 2008

An Efficient Edge-Preserving Algorithm for Removal of Salt-and-Pepper Noise.
IEEE Signal Process. Lett., 2008

A real-time image denoising chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A Low-Cost VLC Implementation for MPEG-4.
IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Low-Complexity Interpolation Method for Deinterlacing.
IEICE Trans. Inf. Syst., 2007

2006
A Low-Cost CAVLC Encoder.
IEICE Trans. Electron., 2006

An Efficient Implementation of CAVLC for H.264/AVC.
Proceedings of the First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August, 2006

2004
An efficient prediction algorithm for image vector quantization.
IEEE Trans. Syst. Man Cybern. Part B, 2004

VLSI Implementation for One-Dimensional Multilevel Lifting-Based Wavelet Transform.
IEEE Trans. Computers, 2004

VLSI Architecture for 2-D 3-Level Lifting-Based Discrete Wavelet Transform.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2004

2003
An index coding algorithm for image vector quantization.
IEEE Trans. Consumer Electron., 2003

2002
A fuzzy search block-matching chip for motion estimation.
Integr., 2002

2001
An efficient blocking-matching algorithm based on fuzzy reasoning.
IEEE Trans. Syst. Man Cybern. Part B, 2001

2000
An adaptive fuzzy logic controller: its VLSI architecture and applications.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Adaptive arithmetic coding using fuzzy reasoning and grey prediction.
Fuzzy Sets Syst., 2000

A fast-search motion estimation method.
Proceedings of the IEEE International Conference on Systems, 2000

A New Search Algorithm for Block Motion Estimation.
Proceedings of the 2000 IEEE International Conference on Multimedia and Expo, 2000

1999
The gray prediction search algorithm for block motion estimation.
IEEE Trans. Circuits Syst. Video Technol., 1999

A fast and efficient lossless data-compression method.
IEEE Trans. Commun., 1999

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999


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