Jer-Min Jou

According to our database1, Jer-Min Jou authored at least 29 papers between 1989 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2014
A Run-time Manager for Multithreading of Multi-core Systems.
Proceedings of the Intelligent Systems and Applications, 2014

A Transaction-based Design Model and Its MPEG-2 Encoder Design.
Proceedings of the Intelligent Systems and Applications, 2014

2011
Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

2010
An Optimal Round-Robin Arbiter Design for NoC.
J. Inf. Sci. Eng., 2010

Efficient design and generation of a multi-facet arbiter.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010

New model-driven design and generation of multi-facet arbiters part I: from the design model to the architecture model.
Proceedings of the 47th Design Automation Conference, 2010

2009
A high-speed and decentralized arbiter design for NoC.
Proceedings of the 7th IEEE/ACS International Conference on Computer Systems and Applications, 2009

2007
A Novel Reconfigurable Computation Unit for DSP Applications.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2005
A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC).
IEICE Transactions, 2005

2004
Efficient Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme.
IEICE Transactions, 2004

2002
Design of a dynamic pipelined architecture for fuzzy color correction.
IEEE Trans. VLSI Syst., 2002

2001
An efficient blocking-matching algorithm based on fuzzy reasoning.
IEEE Trans. Systems, Man, and Cybernetics, Part B, 2001

Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000
An adaptive fuzzy logic controller: its VLSI architecture and applications.
IEEE Trans. VLSI Syst., 2000

Adaptive arithmetic coding using fuzzy reasoning and grey prediction.
Fuzzy Sets Syst., 2000

1999
The gray prediction search algorithm for block motion estimation.
IEEE Trans. Circuits Syst. Video Techn., 1999

A fast and efficient lossless data-compression method.
IEEE Trans. Communications, 1999

A New Pipelined Architecture for Fuzzy Color Correction.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

Hazard-Free Synthesis and Decomposition of Asynchronous Circuits.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997
Diagnostic fault simulation for synchronous sequential circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Serial diagnostic fault simulation for synchronous sequential circuits.
Integr., 1997

1995
Distributed Diagnostic Fault Simulation for Synchronous Sequential Circuits by Dynamic Fault Partitioning.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994
Multiport Memory Based Data Path Allocation Focusing on Interconnection Optimization.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Super Fast & Memory Efficient Diagnostic Simulation Algorithm for Combinatorial Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A fast and memory-efficient diagnostic fault simulation for sequential circuits.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993
Library-Adaptively Integrated Data Path Synthesis for DSP Systems.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1990
An Efficient VLSI Switch-Box Router.
IEEE Design & Test of Computers, 1990

1989
A new 3-layer rectilinear area router with obstacle avoidance.
Integr., 1989


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