Yi Diao

According to our database, Yi Diao authored at least 8 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO.

Xing Wei, Yi Diao, Yu-Liang Wu

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates).

Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

A universal macro block mapping scheme for arithmetic circuits.

Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A coupling area reduction technique applying ODC shifting.

Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire.

Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.

Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2012

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.

Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions.

Yi Diao, Yu-Liang Wu

Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics, 2011