Wai-Chung Tang

According to our database, Wai-Chung Tang authored at least 16 papers between 2005 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2014

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire.

Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only).

Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.

Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme.

Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu

ACM Trans. Design Autom. Electr. Syst., 2012

Postgrid Clock Routing for High Performance Microprocessor Designs.

Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

WRIP: logic restructuring techniques for wirelength-driven incremental placement.

Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Almost every wire is removable: A modeling and solution for removing any circuit wire.

Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.

Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Grid-to-ports clock routing for high performance microprocessor designs.

Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze

Proceedings of the 2011 International Symposium on Physical Design, 2011

On applying erroneous clock gating conditions to further cut down power.

Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010

Logic synthesis for low power using clock gating and rewiring.

Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

2008

Improving FPGA designs with incremental logic resynthesis and shortcut-based routing architecture.

Wai-Chung Tang

PhD thesis, 2008

A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability.

Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu

Proceedings of the 2008 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2008

2007

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring.

Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.

Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu

Proceedings of the 44th Design Automation Conference, 2007

2005

FPGA technology mapping optimization by rewiring algorithms.

Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005