Po-Chiun Huang

Orcid: 0000-0001-5469-3795

According to our database1, Po-Chiun Huang authored at least 50 papers between 1996 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2022

2021
A Cross-Correlation-Based Time-of-Flight Design for Chaos Lidar Systems.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
Portable Sleep Apnea Syndrome Screening and Event Detection Using Long Short-Term Memory Recurrent Neural Network.
Sensors, 2020

2 x 3 Arrayed CMOS Capacitive Biosensors for Detection of microRNAs on a Microfluidic System.
Proceedings of the 15th IEEE International Conference on Nano/Micro Engineered and Molecular System, 2020

2018
Electromagnetic Energy Harvester Interface Design for Wearable Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A Portable Monitoring System with Automatic Event Detection for Sleep Apnea Level-IV Evaluation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Sleep Apnea Detection Based on Thoracic and Abdominal Movement Signals of Wearable Piezoelectric Bands.
IEEE J. Biomed. Health Informatics, 2017

2016
A Battery-Less, Implantable Neuro-Electronic Interface for Studying the Mechanisms of Deep Brain Stimulation in Rat Models.
IEEE Trans. Biomed. Circuits Syst., 2016

Cooperation between Distributed Power Modules for SoC Power Management.
IEICE Trans. Electron., 2016

2015
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 0.003 mm<sup>2</sup> 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching.
IEEE J. Solid State Circuits, 2015

A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics.
IEEE J. Solid State Circuits, 2015

2014
A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A mixed-signal phase-domain FSK demodulator for BLE single-path low-IF receiver.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

28.3 A frequency-defined vernier digital-to-time converter for impulse radar systems in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

An intelligent brain machine interface with wireless micro-stimulation and neural recording.
Proceedings of IEEE-EMBS International Conference on Biomedical and Health Informatics, 2014

A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

A feedforward noise and distortion cancellation technique for CMOS broadband LNA-mixer.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
AC-Plus Scan Methodology for Small Delay Testing and Characterization.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Time-domain analog-to-digital converters with domino delay lines.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

A scalable direct-sampling broadband radar receiver supporting simultaneous digital multibeam array in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

An implantable microsystem for long-term study on the mechanism of deep brain stimulation.
Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012
A Low Cost Calibrated DAC for High-Resolution Video Display System.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A Power-Efficient Noise Suppression Technique Using Signal-Nulled Feedback for Low-Noise Wideband Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A UWB IR timed-array radar using time-shifted direct-sampling architecture.
Proceedings of the Symposium on VLSI Circuits, 2012

A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

An implantable microsystem for studying the Parkinson's Disease.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A low-power CMOS LNA using noise suppression and distortion cancellation techniques with inductive bandwidth extension.
Proceedings of the International SoC Design Conference, 2011

A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing.
Proceedings of the 48th Design Automation Conference, 2011

An asynchronous digitally-controlled switching converter with adaptive resolution and dynamic power saving to achieve higher than 93.5% efficiency between 5mA and 250mA load.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.
IEEE J. Solid State Circuits, 2010

An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems.
IEEE J. Solid State Circuits, 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Design of a process-insensitive digital controller for high-frequency DC-DC SMPS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2008
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

2007
A 1.2-V CMOS Limiter / RSSI / Demodulator for Low-IF FSK Receiver.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A Low-Power CMOS Linear-in-Decibel Variable Gain Amplifier With Programmable Bandwidth and Stable Group Delay.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

Joint Polynomial and Look-Up-Table Predistortion Power Amplifier Linearization.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

An OPLL-DDS based frequency synthesizer for DCS-1800 receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005
Low-power techniques for network security processors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Adaptive I/Q imbalance compensation for RF transceivers.
Proceedings of the Global Telecommunications Conference, 2004. GLOBECOM '04, Dallas, Texas, USA, 29 November, 2004

2001
A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier.
IEEE J. Solid State Circuits, 2001

2000
A 2-V 10.7-MHz CMOS limiting amplifier/RSSI.
IEEE J. Solid State Circuits, 2000

1996
A BiCMOS limiting amplifier for SONET OC-3.
IEEE J. Solid State Circuits, 1996


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