Giacomo Buonanno

According to our database, Giacomo Buonanno authored at least 34 papers between 1990 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Interacting with More Than One Chart: What Is It All About?

Angela Locoro, Paolo Buono, Giacomo Buonanno

Proceedings of the Human-Computer Interaction - INTERACT 2021 - 18th IFIP TC 13 International Conference, Bari, Italy, August 30, 2021

2011

Interorganisational systems within SMEs aggregations: an exploratory study on information requirements of an industrial district.

Federico Pigni, Aurelio Ravarini, Giacomo Buonanno, Donatella Sciuto

Int. J. Inf. Technol. Manag., 2011

2005

Factors affecting ERP system adoption: A comparative analysis between SMEs and large companies.

Giacomo Buonanno, Paolo Faverio, Federico Pigni, Aurelio Ravarini, Donatella Sciuto, Marco Tagliavini

J. Enterp. Inf. Manag., 2005

Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs.

Paolo Faverio, Donatella Sciuto, Giacomo Buonanno

Proceedings of the ICEIS 2005, 2005

Exploring the Role of Inter-Organizational Information Systems within SMEs Aggregations.

Giacomo Buonanno, Federico Pigni, Aurelio Ravarini, Donatella Sciuto

Proceedings of the 18th Bled eConference: eIntegration in Action, 2005

2000

An extended-UIO-based method for protocol conformance testing.

Giacomo Buonanno, Franco Fummi, Donatella Sciuto

J. Syst. Archit., 2000

ICT diffusion and strategic role within Italian SMEs.

Giacomo Buonanno, Stefano Gramignoli, Aurelio Ravarini, Marco Tagliavini, Donatella Sciuto

Proceedings of the Challenges of Information Technology Management in the 21st Century, 2000

1998

Co-Testing: Granting Testability in a Codesign Environment.

Giacomo Buonanno, Mariagiovanna Sami

Integr. Comput. Aided Eng., 1998

Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis.

Marco Broglia, Giacomo Buonanno, Mariagiovanna Sami, M. Selvini

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997

A high-level synthesis approach to design of fault-tolerant systems.

Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.

M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

How an "Evolving" Fault Model Improves the Behavioral Test Generation.

Giacomo Buonanno, Fabrizio Ferrandi, L. Ferrandi, Franco Fummi, Donatella Sciuto

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks.

Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Fault detection and fault tolerance issues at CMOS level through AUED encoding.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

TIES: A testability increase expert system for VLSI design.

Giacomo Buonanno, Franco Fummi, Donatella Sciuto

J. Electron. Test., 1995

A new switching-level approach to multiple-output functions synthesis.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic.

Giacomo Buonanno, Fabio Salice, Donatella Sciuto

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Data Path Testability Analysis Based on BDDs.

Giacomo Buonanno, Fabrizio Ferrandi, Donatella Sciuto

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1994

ALADIN: a multilevel testability analyzer for VLSI system design.

Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza

IEEE Trans. Very Large Scale Integr. Syst., 1994

Innovative Structures for CMOS Combinational Gates Synthesis.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

IEEE Trans. Computers, 1994

CMOS Reliability Improvements Through a New Fault Tolerant Technique.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A CMOS Fault Tolerant Architecture for Swith-Level Faults.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

Fault detection in TFCMOS/DFCMOS combinational gates.

Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Yinan N. Shen

Integr., 1993

New CMOS Structures for the Synthesis of Dominant Functions.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the Sixth International Conference on VLSI Design, 1993

An Expert Solution to Functional Testability Analysis of VLSI Circuits.

Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza

Proceedings of the SEKE'93, 1993

Functional Testing and Constrained Synthesis of Sequential Architectures.

Giacomo Buonanno, Franco Fummi, Donatella Sciuto

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Functional Fault Models and Gate Level Coverage for Sequential Architectures.

Giacomo Buonanno, Franco Fummi, Donatella Sciuto

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Fault Detection in Sequential Circuits through Functional Testing.

Giacomo Buonanno, Franco Fummi, Donatella Sciuto

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.

Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

State assignment and testability of PLA-based finite state machines.

Giacomo Buonanno, Micaela Serra

Microprocess. Microprogramming, 1992

A multi level testability assistant for VLSI design.

Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Donatella Sciuto, Giuseppe Zaza

Proceedings of the conference on European design automation, 1992

1991

Multiple stuck-at faults detection in CMOS combinational gates.

Giacomo Buonanno, Fabrizio Lombardi, Donatella Sciuto, Y.-N. Sken

Microprocessing and Microprogramming, 1991

Optimization techniques for multiple output function synthesis.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the conference on European design automation, 1991

1990

An approach to a design for testability personal consultant.

Giacomo Buonanno, A. Burri, Franco Fummi, Donatella Sciuto

Microprocessing and Microprogramming, 1990