Donatella Sciuto

According to our database1, Donatella Sciuto authored at least 371 papers between 1987 and 2019.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2011, "For contributions to embedded system design".

Timeline

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Bibliography

2019
FPGA-Based Embedded System Implementation of Audio Signal Alignment.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

2018
BuildingRules: A Trigger-Action-Based System to Manage Complex Commercial Buildings.
TCPS, 2018

MARC: A Resource Consumption Modeling Service for Self-Aware Autonomous Agents.
TAAS, 2018

Mine with it or sell it: the superhashing power dilemma.
SIGMETRICS Performance Evaluation Review, 2018

The Case for Polymorphic Registers in Dataflow Computing.
International Journal of Parallel Programming, 2018

HLS Support for Polymorphic Parallel Memories.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Building High-Performance, Easy-to-Use Polymorphic Parallel Memories with HLS.
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018

On How to Efficiently Implement Deep Learning Algorithms on PYNQ Platform.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

FIDA: A Framework to Automatically Integrate FPGA Kernels Within Data-Science Applications.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

A Scalable FPGA Design for Cloud N-Body Simulation.
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017
Optimization Strategies in Design Space Exploration.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

2016
Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices.
ACM Trans. Embedded Comput. Syst., 2016

Efficient Hardware Design of Iterative Stencil Loops.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

State of the Journal.
IEEE Trans. Computers, 2016

On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.
TACO, 2016

Sink state analysis in multi-tenant smart buildings.
Proceedings of the 2nd IEEE International Forum on Research and Technologies for Society and Industry Leveraging a better tomorrow, 2016

EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Resource-Efficient Scheduling for Partially-Reconfigurable FPGA-Based Systems.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Ruleset Minimization in Multi-tenant Smart Buildings.
Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

Danger-system: Exploring new ways to manage occupants safety in smart building.
Proceedings of the 2nd IEEE World Forum on Internet of Things, 2015

Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

BuildingRules: a trigger-action based system to manage complex commercial buildings.
Proceedings of the 2015 ACM International Joint Conference on Pervasive and Ubiquitous Computing and Proceedings of the 2015 ACM International Symposium on Wearable Computers, 2015

OpenMPower: An Open and Accessible Database About Real World Mobile Devices.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Methods and Algorithms for the Interaction of Residential Smart Buildings with Smart Grids.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Experimental Evaluation and Modeling of Thermal Phenomena on Mobile Devices.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Occupancy detection via iBeacon on Android devices for smart building management.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014
A Mapping-Scheduling Algorithm for Hardware Acceleration on Reconfigurable Platforms.
TRETS, 2014

Automated Fine-Grained CPU Provisioning for Virtual Machines.
TACO, 2014

A performance-aware quality of service-driven scheduler for multicore processors.
SIGBED Review, 2014

Looking into the Crystal Ball: From Transistors to the Smart Earth.
IEEE Design & Test, 2014

A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces.
Proceedings of the IEEE World Forum on Internet of Things, 2014

BlueSentinel: a first approach using iBeacon for an energy efficient occupancy detection system.
Proceedings of the 1st ACM Conference on Embedded Systems for Energy-Efficient Buildings, 2014

FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

A Survey on Recent Hardware and Software-Level Cache Management Techniques.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

An Open-Source, Efficient, and Parameterizable Hardware Implementation of the AES Algorithm.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

SPELL: affecting thermal comfort through perceptive techniques.
Proceedings of the 2014 ACM Conference on Ubiquitous Computing, 2014

Improving the security and the scalability of the AES algorithm (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

On How to Design Smart Energy-Efficient Buildings.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

On How to Efficiently Implement Regular Expression Matching on FPGA-Based Systems.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

A Perspective Vision on Complex Residential Building Management Systems.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

On Power and Energy Consumption Modeling for Smart Mobile Devices.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

Effective Reconfigurable Design: The FASTER Approach.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
Adaptive and Flexible Smartphone Power Modeling.
MONET, 2013

A Simulation-Based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs.
IJERTCS, 2013

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms.
IEEE Design & Test, 2013

Dataflow computing with Polymorphic Registers.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

A Flexible Interconnection Structure for Reconfigurable FPGA Dataflow Applications.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

HERA Project's Holistic Evolutionary Framework.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

The FASTER vision for designing dynamically reconfigurable systems.
Proceedings of 2013 International Conference on IC Design & Technology, 2013

MPower: gain back your android battery life!
Proceedings of the 2013 ACM International Joint Conference on Pervasive and Ubiquitous Computing, 2013

Morphone.OS: Context-Awareness in Everyday Life.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Coloring the cloud for predictable performance.
Proceedings of the ACM Symposium on Cloud Computing, SOCC '13, 2013

Towards a performance-as-a-service cloud.
Proceedings of the ACM Symposium on Cloud Computing, SOCC '13, 2013

A2B: An integrated framework for designing heterogeneous and reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

On self-adaptive resource allocation through reinforcement learning.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Ant Colony Optimization for mapping, scheduling and placing in reconfigurable systems.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

ThermOS: System support for dynamic thermal management of chip multi-processors.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
On the Evolution of Hardware Circuits via Reconfigurable Architectures.
TRETS, 2012

TaBit: A framework for task graph to bitstream generation.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Smart technologies for effective reconfiguration: The FASTER approach.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Automatic run-time manager generation for reconfigurable MPSoC architectures.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

A Framework for Thermal and Performance Management.
Proceedings of the 2012 Workshop on Managing Systems Automatically and Dynamically, 2012

Model-based design for wireless body sensor network nodes.
Proceedings of the 13th Latin American Test Workshop, 2012

An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Mini-Robot's Performance Optimization via Online Reconfiguration and HW/SW Task Scheduling.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

DGECS: Description Generator for Evolved Circuits Synthesis.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

On the automatic integration of hardware accelerators into FPGA-based embedded systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

An open-source design and validation platform for reconfigurable systems.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Automated real-time atrial fibrillation detection on a wearable wireless sensor platform.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Energy-Aware FPGA-based Architecture for Wireless Sensor Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

On the Development of a Runtime Reconfigurable Multicore System-on-Chip.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

An adaptive approach for online fault management in many-core architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Metronome: operating system level performance management via self-adaptive computing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

MPower: Towards an Adaptive Power Management System for Mobile Devices.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Knowledge-based design space exploration of wireless sensor networks.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks.
Proceedings of the 2012 Ninth International Conference on Wearable and Implantable Body Sensor Networks, 2012

2011
Applying dynamic reconfiguration in the mobile robotics domain: A case study on computer vision algorithms.
TRETS, 2011

A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Floorplacement for Partial Reconfigurable FPGA-Based Systems.
Int. J. Reconfig. Comp., 2011

Interorganisational systems within SMEs aggregations: an exploratory study on information requirements of an industrial district.
IJITM, 2011

Island-Based Adaptable Embedded System Design.
Embedded Systems Letters, 2011

Dedicated hardware accelerators for the epistatic analysis of human genetic data.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

ReBit: A Tool to Manage and Analyse FPGA-Based Reconfigurable Systems.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

An efficient Quantum-Dot Cellular Automata adder.
Proceedings of the Design, Automation and Test in Europe, 2011

A design methodology to implement memory accesses in high-level synthesis.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

HERA: Hardware evolution over reconfigurable architectures.
Proceedings of the 1st International Workshop on Computing in Heterogeneous, 2011

Emulating Transactional Memory on FPGA Multiprocessors.
Proceedings of the Architecture of Computing Systems - ARCS 2011, 2011

2010
Placement and Floorplanning in Dynamically Reconfigurable FPGAs.
TRETS, 2010

Ant Colony Heuristic for Mapping and Scheduling Tasks and Communications on Heterogeneous Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Decision-Theoretic Design Space Exploration of Multiprocessor Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Guest Editors' Introduction: Special Section on System-Level Design of Reliable Architectures.
IEEE Trans. Computers, 2010

HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms.
IEEE Micro, 2010

A design workflow for dynamically reconfigurable multi-FPGA systems.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A direct bitstream manipulation approach for Virtex4-based evolvable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Run-time mapping of applications on FPGA-based reconfigurable systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Wirelength driven floorplacement for FPGA-based partial reconfigurable systems.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

A novel design framework for the design of reconfigurable systems based on NoCs.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Multiprocessor systems-on-chip synthesis using multi-objective evolutionary computation.
Proceedings of the Genetic and Evolutionary Computation Conference, 2010

A Compact Transactional Memory Multiprocessor System on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Operating system runtime management of partially dynamically reconfigurable embedded systems.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

A reconfigurable multiprocessor architecture for a reliable face recognition implementation.
Proceedings of the Design, Automation and Test in Europe, 2010

Efficient pattern matching on GPUs for intrusion detection systems.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration.
IEEE Trans. VLSI Syst., 2009

Partitioning and Scheduling of Task Graphs on Partially Dynamically Reconfigurable FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

ReSP: A Nonintrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A Transform-Parametric Approach to Boolean Matching.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

A Highly Parallel FPGA-based Evolvable Hardware Architecture.
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009

A multiprocessor self-reconfigurable JPEG2000 encoder.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

On-line task management for a reconfigurable cryptographic architecture.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems.
Proceedings of the Genetic and Evolutionary Computation Conference, 2009

A runtime relocation based workflow for self dynamic reconfigurable systems design.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

HW/SW methodologies for synchronization in FPGA multiprocessors.
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

A real-time application design methodology for MPSoCs.
Proceedings of the Design, Automation and Test in Europe, 2009

Mapping pipelined applications onto heterogeneous embedded systems: a bayesian optimization algorithm based approach.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

Prototyping pipelined applications on a heterogeneous FPGA multiprocessor virtual platform.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

An application-centered design flow for self reconfigurable systems implementation.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Static Analysis of Transaction-Level Communication Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Improving evolutionary exploration to area-time optimization of FPGA designs.
Journal of Systems Architecture - Embedded Systems Design, 2008

Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electronic Testing, 2008

Reconfigurable Computing and Hardware/Software Codesign.
EURASIP J. Emb. Sys., 2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

A light-weight Network-on-Chip architecture for dynamically reconfigurable systems.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Core Allocation and Relocation Management for a Self Dynamically Reconfigurable Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

A Multi-objective Genetic Algorithm for Design Space Exploration in High-Level Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

A design flow tailored for self dynamic reconfigurable architecture.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Operating system support for online partial dynamic reconfiguration management.
Proceedings of the FPL 2008, 2008

An architecture for dynamically reconfigurable real time audio processing systems.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

Fault Models and Injection Strategies in SystemC Specifications.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Generation Flow for Self-Reconfiguration Controllers Customization.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications.
Proceedings of the Design, Automation and Test in Europe, 2008

Task Scheduling with Configuration Prefetching and Anti-Fragmentation techniques on Dynamically Reconfigurable Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

Concurrency emulation and analysis of parallel applications for multi-processor system-on-chip co-design.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008

The Shining embedded system design methodology based on self dynamic reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Lightweight DMA management mechanisms for multiprocessors on FPGA.
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

High-Level Modeling and Exploration of Reconfigurable MPSoCs.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference].
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Multi-Accuracy Power and Performance Transaction-Level Modeling.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An adaptive genetic algorithm for dynamically reconfigurable modules allocation.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

An Interrupt Controller for FPGA-based Multiprocessors.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

An Evolutionary Approach to Area-Time Optimization of FPGA designs.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAsb.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Dynamic Reconfigurability in Embedded System Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs.
Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

A novel SoC design methodology combining adaptive software and reconfigurable hardware.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A design kit for a fully working shared memory multiprocessor on FPGA.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

An efficient cost-based canonical form for Boolean matching.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-Chip.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

A Unified Approach to Canonical Form-based Boolean Matching.
Proceedings of the 44th Design Automation Conference, 2007

Fitness inheritance in evolutionary and multi-objective high-level synthesis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007

A Self-Reconfigurable Implementation of the JPEG Encoder.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC.
IEEE Trans. Computers, 2006

Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.
Proceedings of the IFIP VLSI-SoC 2006, 2006

An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA.
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Automatic Test Pattern Generation with BOA.
Proceedings of the Parallel Problem Solving from Nature, 2006

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Partial Dynamic Reconfiguration: The Caronte Approach. A New Degree of Freedom in the HW/SW Codesign.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Synthesis of Object Oriented Models on Reconfigurable Hardware.
Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Combined software and hardware techniques for the design of reliable IP processors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Exploiting TLM and object introspection for system-level simulation.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Decision-theoretic exploration of multiProcessor platforms.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Using speculative computation and parallelizing techniques to improve scheduling of control based designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Factors affecting ERP system adoption: A comparative analysis between SMEs and large companies.
J. Enterprise Inf. Management, 2005

A Framework for the Functional Verification of SystemC Models.
International Journal of Parallel Programming, 2005

Reducing the complexity of instruction-level power models for VLIW processors.
Design Autom. for Emb. Sys., 2005

Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Operating system support for dynamically reconfigurable SoC architectures.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs.
Proceedings of the ICEIS 2005, 2005

Mapping Interface Method Calls over OCP Buses.
Proceedings of the Forum on specification and Design Languages, 2005

Aspect Orientation in System Level Design.
Proceedings of the Forum on specification and Design Languages, 2005

Caronte: A Complete Methodology for the Implementation of Partially Dynamically Self-Reconfiguring Systems on FPGA Platforms.
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

A Data Oriented Approach to the Design of Reconfigurable Stream Decoders.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

A model of soft error effects in generic IP processors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

Reliable System Specification for Self-Checking Data-Paths.
Proceedings of the 2005 Design, 2005

Exploring the Role of Inter-Organizational Information Systems within SMEs Aggregations.
Proceedings of the 18th Bled eConference: eIntegration in Action, 2005

2004
Virtual Community in the Classroom: An Innovating Tool for Elearning.
Proceedings of the EDUTECH, 2004

System Level Hardware-Software Design Exploration with XCS.
Proceedings of the Genetic and Evolutionary Computation, 2004

Reliable System Co-Design: The FIR Case Study.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

System-level metrics for hardware/software architectural mapping.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Synthesis of Dynamic Class Loading Specifications on Reconfigurable Hardware.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

SystemC and SystemVerilog: Where do They Fit? Where are They Going?
Proceedings of the 2004 Design, 2004

Analysis and Modeling of Energy Reducing Source Code Transformations.
Proceedings of the 2004 Design, 2004

Plug-in of power models in the StepNP exploration platform: analysis of power/performance trade-offs.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Identification of design errors through functional testing.
IEEE Trans. Reliability, 2003

The design of reliable devices for mission-critical applications.
IEEE Trans. Instrumentation and Measurement, 2003

A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems.
Proceedings of the 2003 ACM Symposium on Applied Computing (SAC), 2003

An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System.
Proceedings of the Forum on specification and Design Languages, 2003

An Integrated Design Approach for Self-Checking FPGAs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Transaction Based Design: Another Buzzword or the Solution to a Design Problem?
Proceedings of the 2003 Design, 2003

Library Functions Timing Characterization for Source-Level Analysis.
Proceedings of the 2003 Design, 2003

Static analysis of transaction-level models.
Proceedings of the 40th Design Automation Conference, 2003

2002
Low-power data forwarding for VLIW embedded architectures.
IEEE Trans. VLSI Syst., 2002

An instruction-level energy model for embedded VLIW architectures.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Static power modeling of 32-bit microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Test Generation and Testability Alternatives Exploration of Critical Algorithms for Embedded Applications.
IEEE Trans. Computers, 2002

Behavioral test generation for the selection of BIST logic.
Journal of Systems Architecture, 2002

The Impact of Source Code Transformations on Software Power and Energy Consumption.
Journal of Circuits, Systems, and Computers, 2002

Reliability Properties Assessment at System Level: A Co-Design Framework.
J. Electronic Testing, 2002

A Sensitivity-Based Design Space Exploration Methodology for Embedded Systems.
Design Autom. for Emb. Sys., 2002

Modeling Assembly Instruction Timing in Superscalar Architectures.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Designing Self-Checking FPGAs through Error Detection Codes.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

Functional Verification for SystemC Descriptions Using Constraint Solving.
Proceedings of the 2002 Design, 2002

Error Simulation Based on the SystemC Design Description Language.
Proceedings of the 2002 Design, 2002

An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores.
Proceedings of the 2002 Design, 2002

Energy estimation and optimization of embedded VLIW processors based on instruction clustering.
Proceedings of the 39th Design Automation Conference, 2002

Metrics for design space exploration of heterogeneous multiprocessor embedded systems.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

2001
An efficient heuristic approach to solve the unate covering problem.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Pursuing coherence in software process assessment and improvement.
Software Process: Improvement and Practice, 2001

On-line fault detection in a hardware/software co-design environment.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Dynamic modeling of inter-instruction effects for execution time estimation.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Fast system-level exploration of memory architectures driven by energy-delay metrics.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Designing Reliable Embedded Systems Based on 32 Bit Microprocessors.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

An Assembly-Level Execution-Time Model for Pipelined Architectures.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Exploiting data forwarding to reduce the power budget of VLIW embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Functional test generation for behaviorally sequential models.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

A design framework to efficiently explore energy-delay tradeoffs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Source-level execution time estimation of C programs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Design of VHDL-based totally self-checking finite-state machine and data-path descriptions.
IEEE Trans. VLSI Syst., 2000

Symbolic optimization of interacting controllers based onredundancy identification and removal.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

A Hierarchical Test Generation Approach for Large Controllers.
IEEE Trans. Computers, 2000

An extended-UIO-based method for protocol conformance testing.
Journal of Systems Architecture, 2000

Guest Editor's Introduction: Design Tools for Embedded Systems.
IEEE Design & Test of Computers, 2000

Testability Alternatives Exploration through Functional Testing.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

A Multi-Level Strategy for Software Power Estimation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

ICT diffusion and strategic role within Italian SMEs.
Proceedings of the Challenges of Information Technology Management in the 21st Century, 2000

An Application of Genetic Algorithms and BDDs to Functional Testing.
Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

Power Exploration for Embedded VLIW Architectures.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

An approach to functional testing of VLIW architectures.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000

BIST Architectures Selection Based on Behavioral Testing.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

An instruction-level functionally-based energy estimation model for 32-bits microprocessors.
Proceedings of the 37th Conference on Design Automation, 2000

Instruction-level power estimation for embedded VLIW cores.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Power optimization of system-level address buses based on software profiling.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

Energy estimation for 32-bit microprocessors.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Synthesis for Testability of Highly Complex Controllers by Functional Redundancy Removal.
IEEE Trans. Computers, 1999

Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study.
Proceedings of the IEEE International Conference On Computer Design, 1999

Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

A Synthesis Methodology Aimed at Improving the Quality of TSC Devices.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems.
Proceedings of the 1999 Design, 1999

Symbolic Functional Vector Generation for VHDL Specifications.
Proceedings of the 1999 Design, 1999

Power estimation for architectural exploration of HW/SW communication on system-level buses.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

HW/SW Co-design of Embedded Systems.
Proceedings of the Reliable Software Technologies, 1999

1998
Automatic generation of error control codes for computer applications.
IEEE Trans. VLSI Syst., 1998

Power estimation of embedded systems: a hardware/software codesign approach.
IEEE Trans. VLSI Syst., 1998

Testability analysis and behavioral testing of the Hopfield neural paradigm.
IEEE Trans. VLSI Syst., 1998

Clock skew reduction in ASIC logic design: a methodology for clock tree management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Partitioning of Hardware-Software Embedded Systems: A Metrics-based Approach.
Integrated Computer-Aided Engineering, 1998

Fault Analysis for Networks with Concurrent Error Detection.
IEEE Design & Test of Computers, 1998

Implicit test generation for behavioral VHDL models.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Concurrent Error Detection at Architectural Level.
Proceedings of the 11th International Symposium on System Synthesis, 1998

Automatic VHDL restructuring for RTL synthesis optimization and testability improvement.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

System-level performance estimation strategy for sw and hw.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

VHDL Testability Analysis Based on Fault Clustering and Implicit Fault Injection.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Systematic AUED Codes for Self-Checking Architectures.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Fault Analysis in Networks with Concurrent Error Detection Properties.
Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.
Proceedings of the 1998 Design, 1998

A Model for System-Level Timed Analysis and Profiling.
Proceedings of the 1998 Design, 1998

1997
Functional design for testability of control-dominated architectures.
ACM Trans. Design Autom. Electr. Syst., 1997

Special section on VHDL.
Journal of Systems Architecture, 1997

A VHDL-based approach for power estimation of embedded systems.
Journal of Systems Architecture, 1997

A complete testing strategy based on interacting and hierarchical FSMs.
Integration, 1997

Testing Core-Based Systems: A Symbolic Methodology.
IEEE Design & Test of Computers, 1997

A Two-Level Cosimulation Environment.
IEEE Computer, 1997

Implicit test pattern generation constrained to cellular automata embedding.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A TSC Evaluation Function for Combinational Circuits.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

How an "Evolving" Fault Model Improves the Behavioral Test Generation.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Parity Bit Code: Achieving a Complete Fault Coverage in the Design of TSC Combinational Networks.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Designing Networks with Error Detection Properties through the Fault-Error Relation.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks.
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

A novel methodology for designing TSC networks based on the parity bit code.
Proceedings of the European Design and Test Conference, 1997

A Flexible Model for Evaluating the Behavior of Hardware/Software Systems.
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997

1996
VHDL( VHSIC Hardware Description Language).
Journal of Systems Architecture, 1996

FsmTest: Functional test generation for sequential circuits.
Integration, 1996

Co-synthesis and co-simulation of control-dominated embedded systems.
Design Autom. for Emb. Sys., 1996

The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Test Generation for Networks of Interacting FSMs Using Symbolic Techniques.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

Software methodologies for VHDL code static analysis based on flow graphs.
Proceedings of the conference on European design automation, 1996

BDD-based testability estimation of VHDL designs.
Proceedings of the conference on European design automation, 1996

Redundant Faults in TSC Networks: Definition and Removal.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Fault detection and fault tolerance issues at CMOS level through AUED encoding.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

A Parametric Design of a Built-in Self-Test FIFO Embedded Memory.
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques.
Proceedings of the 33st Conference on Design Automation, 1996

Partitioning and Exploration Strategies in the TOSCA Co-Design Flow.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1995
Construction techniques for systematic SEC-DED codes with single byte error detection and partial correction capability for computer memory systems.
IEEE Trans. Information Theory, 1995

Testability of artificial neural networks: A behavioral approach.
J. Electronic Testing, 1995

A new DFT methodology for sequential circuits.
J. Electronic Testing, 1995

TIES: A testability increase expert system for VLSI design.
J. Electronic Testing, 1995

VLSI design of systematic odd-weight-column byte error detecting SEC-DED codes.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A new switching-level approach to multiple-output functions synthesis.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

GECO: A Tool for Automatic Generation of Error Control Codes for Computer Applications.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Data Path Testability Analysis Based on BDDs.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

An Output/State Encoding for Self-Checking Finite State Machine.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Synthesis for testability of large complexity controllers.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

Testable synthesis of high complex control devices.
Proceedings of the Proceedings EURO-DAC'95, 1995

Self-checking FSMs based on a constant distance state encoding.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Sequential logic minimization based on functional testability.
Proceedings of the 1995 European Design and Test Conference, 1995

Automatic clock tree generation in ASIC designs.
Proceedings of the 1995 European Design and Test Conference, 1995

1994
ALADIN: a multilevel testability analyzer for VLSI system design.
IEEE Trans. VLSI Syst., 1994

Innovative Structures for CMOS Combinational Gates Synthesis.
IEEE Trans. Computers, 1994

Constraint Generation & Placement for Automatic Layout Design of Analog Integrated Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Two-Dimensional Sequential Array Architectures: Design for Testability Approaches.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

CMOS Reliability Improvements Through a New Fault Tolerant Technique.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

HW/SW Codesign for Embedded Telecom Systems.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

The role of VHDL within the TOSCA hardware/software codesign framework.
Proceedings of the Proceedings EURO-DAC'94, 1994

A Functional Approach to Delay Faults Test Generation for Sequential Circuits.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

From Behavioral Description to Systolic Array Based Architectures.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Synthesis of Multi-level Self-Checking Logic.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

A CMOS Fault Tolerant Architecture for Swith-Level Faults.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

A methodology for control-dominated systems codesign.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Concurrently self-checking structures for Fsms.
Microprocessing and Microprogramming, 1993

Fault detection in TFCMOS/DFCMOS combinational gates.
Integration, 1993

New CMOS Structures for the Synthesis of Dominant Functions.
Proceedings of the Sixth International Conference on VLSI Design, 1993

An Expert Solution to Functional Testability Analysis of VLSI Circuits.
Proceedings of the SEKE'93, 1993

Functional Testing and Constrained Synthesis of Sequential Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Functional Fault Models and Gate Level Coverage for Sequential Architectures.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

On the minimal test set for single fault location.
Proceedings of the European Design Automation Conference 1993, 1993

Fault Detection in Sequential Circuits through Functional Testing.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
A behavioral approach to testability analysis for neural networks.
Microprocessing and Microprogramming, 1992

Constant testability of combinational cellular tree structures.
J. Electronic Testing, 1992

A multi level testability assistant for VLSI design.
Proceedings of the conference on European design automation, 1992

1991
Testing and diagnosis ofFFT arrays.
VLSI Signal Processing, 1991

Testability conditions for two-dimensional bilateral arrays.
Integration, 1991

Protocol Conformance Testing by Discriminating UIO Sequences.
Proceedings of the Protocol Specification, 1991

Optimization techniques for multiple output function synthesis.
Proceedings of the conference on European design automation, 1991

1990
Evaluation and improvement of fault coverage for verification and validation of protocols.
Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing, 1990

A Routing Algorithm for Harvesting Multipipeline Arrays with Small Intercell and Pipeline Delays.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

1989
Functional testing and verification of array systems.
Microprocessors and Microsystems - Embedded Hardware Design, 1989

1988
An algorithm for functional reconfiguration of fixed-size arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

On Functional Testing of Array Processors.
IEEE Trans. Computers, 1988

1987
A Technique for Reconfiguring Two Dimensional VLSI Arrays.
Proceedings of the 8th IEEE Real-Time Systems Symposium (RTSS '87), 1987


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