Yirong Kan

According to our database, Yirong Kan authored at least 26 papers between 2020 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

FPSpike: A Fully Parallel and Reconfigurable Architecture for Accelerating Spiking Neural Networks With Structured Sparsity.

Mingyang Li, Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2026

DystoHD: an area-efficient hyperdimensional computing system with dynamic hypervector generation for memory-constrained devices.

Haoyu Tang, Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima

J. Supercomput., February, 2026

An FPGA Accelerator for Vision Transformer with Quantization and LUT-Based Operations.

Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

IEICE Trans. Inf. Syst., 2026

Efficient Hardware Implementation of Robust Binary Neural Networks Using End-to-End Unipolar Representation.

Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2026

Mutual Information Loss for Enhancing Class-Wise Representation in Spiking Neural Networks.

Yiling Yang, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the IEEE International Symposium on Circuits and Systems, 2026

2025

Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits.

Rongliang Fu, Mengmeng Wang, Yirong Kan, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

A DNN-Oriented Rapid Simulation Framework for Digital Processing-In-Memory Architectures.

Yirong Kan, Guangxian Zhu, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 38th IEEE International System-on-Chip Conference, 2025

A Lightweight Transformer Model with Dynamic Sparse Mask for Neural Machine Translation.

Nastaran Asadi, Babak Golbabaei, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the IEEE Symposium on Low-Power and High-Speed Chips and Systems, 2025

2024

Bisection Neural Network Toward Reconfigurable Hardware Implementation.

Yan Chen, Renyuan Zhang, Yirong Kan, Sa Yang, Yasuhiko Nakashima

IEEE Trans. Neural Networks Learn. Syst., March, 2024

A Fully-Parallel Reconfigurable Spiking Neural Network Accelerator with Structured Sparse Connections.

Mingyang Li, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Power-Efficient Acceleration of GCNs on Coarse-Grained Linear Arrays.

Dohyun Kim, Koki Asahina, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2024

An FPGA-Oriented Quantization Approach for Vision Transformer with LUT-Friendly Operations.

Cheng Xu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the Twelfth International Symposium on Computing and Networking, 2024

2023

A Low Latency Spiking Neural Network with Improved Temporal Dynamics.

Yunpeng Yao, Yirong Kan, Guangxian Zhu, Renyuan Zhang

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks.

Babak Golbabaei, Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

An Ultra-Compact Calculation Unit with Temporal-Spatial Re-configurability.

Guangxian Zhu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits.

Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Computer-Aided-Prediction of Body Constitution with Efficient Cock-Tail Learning.

Guang Shi, Yirong Kan, Renyuan Zhang

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network.

Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Online Learning of Parameters for Modeling User Preference Based on Bayesian Network.

Yirong Kan, Kun Yue, Hao Wu, Xiaodong Fu, Zhengbao Sun

Int. J. Uncertain. Fuzziness Knowl. Based Syst., 2022

A Stochastic Coding Method of EEG Signals for Sleep Stage Classification.

Guangxian Zhu, Huijia Wang, Yirong Kan, Zheng Chen, Ming Huang, Md. Altaf-Ul-Amin, Naoaki Ono, Shigehiko Kanaya, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

GAND-Nets: Training Deep Spiking Neural Networks with Ternary Weights.

Man Wu, Yirong Kan, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Adaptive Spike-Like Representation of EEG Signals for Sleep Stages Scoring.

Lingwei Zhu, Ziwei Yang, Koki Odani, Guang Shi, Yirong Kan, Zheng Chen, Renyuan Zhang

Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

Automatic Sleep Staging via Frequency-Wise Spiking Neural Networks.

Haohui Jia, Ziwei Yang, Pei Gao, Man Wu, Chen Li, Yirong Kan, Renyuan Zhang

Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2022

2021

DiaNet: An elastic neural network for effectively re-configurable implementation.

Man Wu, Yirong Kan, Tati Erlina, Renyuan Zhang, Yasuhiko Nakashima

Neurocomputing, 2021

2020

An Elastic Neural Network Toward Multi-Grained Re-configurable Accelerator.

Man Wu, Yan Chen, Yirong Kan, Takeshi Nomura, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

A Multi-grained Reconfigurable Accelerator for Approximate Computing.

Yirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020