Rongliang Fu

Orcid: 0000-0003-3744-2083

According to our database¹, Rongliang Fu authored at least 30 papers between 2020 and 2026.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Book In proceedings Article PhD thesis Dataset Other

Bibliography

2026

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation.

[BibT_eX]

[DOI]

CoRR, May, 2026

MappingEvolve: LLM-Driven Code Evolution for Technology Mapping.

[BibT_eX]

[DOI]

CoRR, April, 2026

AstroVLM: Expert Multi-agent Collaborative Reasoning for Astronomical Imaging Quality Diagnosis.

[BibT_eX]

[DOI]

CoRR, April, 2026

Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design.

[BibT_eX]

[DOI]

CoRR, February, 2026

JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, January, 2026

Partitioning-free 3D-IC Floorplanning.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

DCLOG: Don't Cares-based Logic Optimization using Pre-training Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st Asia and South Pacific Design Automation Conference, 2026

2025

Efficient Cartesian Genetic Programming-Based Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2025

TeMACLE: A Technology Mapping-Aware Area-Efficient Standard Cell Library Extension Framework.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2025

Buffer and Splitter Insertion for Adiabatic Quantum-Flux-Parametron Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2025

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning.

[BibT_eX]

[DOI]

Proceedings of the 2025 International Symposium on Physical Design, 2025

JBSA: A Bit-Serial Accelerator for Deep Neural Networks Using Superconducting SFQ Logic.

[BibT_eX]

[DOI]

Proceedings of the 39th ACM International Conference on Supercomputing, 2025

ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

An Optimal DFF-Oriented Technology Legalization Algorithm for Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2025, GLSVLSI 2025, New Orleans, LA, USA, 30 June 2025, 2025

SeDA: Secure and Efficient DNN Accelerators with Hardware/Software Synergy.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

Late Breaking Results: Hybrid Logic Optimization with Predictive Self-Supervision.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

FlatDD: A High-Performance Quantum Circuit Simulator using Decision Diagram and Flat Array.

[BibT_eX]

[DOI]

Proceedings of the 53rd International Conference on Parallel Processing, 2024

RABER: Reliability-Aware Bayesian-Optimization-based Control Layer Escape Routing for Flow-based Microfluidics.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

JPlace: A Clock-Aware Length-Matching Placement for Rapid Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

RCGP: An Automatic Synthesis Framework for Reversible Quantum-Flux-Parametron Logic Circuits based on Efficient Cartesian Genetic Programming.

[BibT_eX]

[DOI]

Rongliang Fu

Robert Wille

Tsung-Yi Ho

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

A survey on superconducting computing technology: circuits, architectures and design tools.

[BibT_eX]

[DOI]

CCF Trans. High Perform. Comput., 2022

2021

Equivalence Checking for Superconducting RSFQ Logic Circuits.

[BibT_eX]

[DOI]

Rongliang Fu

Junying Huang

Zhimin Zhang

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Rongliang Fu

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