Rongliang Fu

According to our database, Rongliang Fu authored at least 9 papers between 2020 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

DLPlace: A Delay-Line Clocking-Based Placement Framework for AQFP Circuits.

Rongliang Fu, Olivia Chen, Bei Yu, Nobuyuki Yoshikawa, Tsung-Yi Ho

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Exact Logic Synthesis for Reversible Quantum-Flux-Parametron Logic.

Rongliang Fu, Olivia Chen, Nobuyuki Yoshikawa, Tsung-Yi Ho

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

JRouter: A Multi-Terminal Hierarchical Length-Matching Router under Planar Manhattan Routing Model for RSFQ Circuits.

Xinda Chen, Rongliang Fu, Junying Huang, Huawei Cao, Zhimin Zhang, Xiaochun Ye, Tsung-Yi Ho, Dongrui Fan

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

BOMIG: A Majority Logic Synthesis Framework for AQFP Logic.

Rongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu, Tsung-Yi Ho, Olivia Chen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Global Optimization Algorithm for Buffer and Splitter Insertion in Adiabatic Quantum-Flux-Parametron Circuits.

Rongliang Fu, Mengmeng Wang, Yirong Kan, Nobuyuki Yoshikawa, Tsung-Yi Ho, Olivia Chen

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits.

Rongliang Fu, Junying Huang, Haibin Wu, Xiaochun Ye, Dongrui Fan, Tsung-Yi Ho

IEEE Trans. Computers, 2022

A survey on superconducting computing technology: circuits, architectures and design tools.

Junying Huang, Rongliang Fu, Xiaochun Ye, Dongrui Fan

CCF Trans. High Perform. Comput., 2022

2021

Equivalence Checking for Superconducting RSFQ Logic Circuits.

Rongliang Fu, Junying Huang, Zhimin Zhang

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits.

Rongliang Fu, Zhimin Zhang, Guang-Ming Tang, Junying Huang, Xiaochun Ye, Dongrui Fan, Ninghui Sun

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020