Yasuhiko Nakashima
Orcid: 0000-0002-9457-5061
According to our database1,
Yasuhiko Nakashima
authored at least 140 papers
between 1995 and 2024.
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Bibliography
2024
IEEE Trans. Neural Networks Learn. Syst., March, 2024
IEEE Micro, 2024
Flexible and Energy-Efficient Crypto-Processor for Arbitrary Input Length Processing in Blockchain-Based IoT Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
2023
Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications.
IEEE Des. Test, October, 2023
Implementation of Fully-Pipelined CNN Inference Accelerator on FPGA and HBM2 Platform.
IEICE Trans. Inf. Syst., June, 2023
IEEE Trans. Neural Networks Learn. Syst., May, 2023
Time-domain Subtractive Readout Scheme for Scalable Capacitive Analog In-Memory Computing.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
A Non-deterministic Training Approach for Memory-Efficient Stochastic Neural Networks.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Small-Footprint Reconfigurable Heterogeneous Cryptographic Accelerator for Fog Computing.
Proceedings of the International Conference on Computing and Communication Technologies, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Energy-Efficient Unified Multi-Hash Coprocessor for Securing IoT Systems Integrating Blockchain.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
High-efficiency Reconfigurable Crypto Accelerator Utilizing Innovative Resource Sharing and Parallel Processing.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
Universal 32/64-bit CGRA for Lightweight Cryptography in Securing IoT Data Transmission.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023
RHCP: A Reconfigurable High-efficient Cryptographic Processor for Decentralized IoT Platforms.
Proceedings of the 15th International Conference on Knowledge and Systems Engineering, 2023
Proceedings of the International Conference on IC Design and Technology, 2023
Phase-Change Memory using Cu2GeTe3 and Multiple Writing Technique for Neuromorphic Systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2023
Proceedings of the Eleventh International Symposium on Computing and Networking, CANDAR 2023, Matsue, Japan, November 28, 2023
2022
MuGRA: A Scalable Multi-Grained Reconfigurable Accelerator Powered by Elastic Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEICE Trans. Inf. Syst., 2022
IEICE Trans. Inf. Syst., 2022
IEEE Access, 2022
IEEE Access, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Application and Evaluation of Quantization for Narrow Bit-width Resampling of Sequential Monte Carlo.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
A Flexible and Energy-Efficient BLAKE-256/2s Co-Processor for Blockchain-based IoT Applications.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022
2021
BCA: A 530-mW Multicore Blockchain Accelerator for Power-Constrained Devices in Securing Decentralized Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Efficient hardware task migration for heterogeneous FPGA computing using HDL-based checkpointing.
Integr., 2021
Neurocomputing, 2021
IEICE Trans. Inf. Syst., 2021
IEICE Trans. Electron., 2021
IEEE Access, 2021
MRSA: A High-Efficiency Multi ROMix Scrypt Accelerator for Cryptocurrency Mining and Data Security.
IEEE Access, 2021
An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Preliminary Evaluation for Multi-domain Spike Coding on Memcapacitive Neuromorphic Circuit.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021
Proceedings of the Ninth International Symposium on Computing and Networking, 2021
Proceedings of the Ninth International Symposium on Computing and Networking, 2021
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2021
2020
Construction of an Efficient Divided/Distributed Neural Network Model Using Edge Computing.
IEICE Trans. Inf. Syst., 2020
Daisy-Chained Systolic Array and Reconfigurable Memory Space for Narrow Memory Bandwidth.
IEICE Trans. Inf. Syst., 2020
Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining.
IEEE Access, 2020
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
A Compact and Accuracy-Reconfigurable Univariate RBF Kernel Based on Stochastic Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the Eighth International Symposium on Computing and Networking, 2020
Proceedings of the Eighth International Symposium on Computing and Networking Workshops, 2020
2019
Programmable Analog Calculation Unit with Two-Stage Architecture: A Solution of Efficient Vector-Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
A ReRAM-Based Row-Column-Oriented Memory Architecture for Convolutional Neural Networks.
IEICE Trans. Electron., 2019
An efficient ReRAM-based inference accelerator for convolutional neural networks via activation reuse.
IEICE Electron. Express, 2019
Non-RLL DC-Balance based on a Pre-scrambled Polar Encoder for Beacon-based Visible Light Communication Systems.
CoRR, 2019
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Evaluation of Neuromorphic Hardware using Cellular Neural Networks and Oxide Semiconductors.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019
Neuro-inspired System with Crossbar Array of Amorphous Metal-Oxide-Semiconductor Thin-Film Devices as Self-plastic Synapse Units.
Proceedings of the Neural Information Processing - 26th International Conference, 2019
Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah.
Proceedings of the 7th International Conference on Communications and Broadband Networking, 2019
Proceedings of the IEEE International Conference on Blockchain and Cryptocurrency, 2019
Proceedings of the 2019 Seventh International Symposium on Computing and Networking, 2019
A Programmable Approximate Calculation Unit Employing Time-Encoded Stochastic Computing Elements.
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019
Proceedings of the Seventh International Symposium on Computing and Networking Workshops, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Run-Length Limited Decoding for Visible Light Communications: A Deep Learning Approach.
Proceedings of the 25th Asia-Pacific Conference on Communications, 2019
2018
Design of Programmable Analog Calculation Unit by Implementing Support Vector Regression for Approximate Computing.
IEEE Micro, 2018
IEICE Trans. Inf. Syst., 2018
Log-Likelihood Ratio Calculation Using 3-Bit Soft-Decision for Error Correction in Visible Light Communication Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Hardware Implementation of A Non-RLL Soft-decoding Beacon-based Visible Light Communication Receiver.
CoRR, 2018
Hopfield Neural Network with Double-Layer Amorphous Metal-Oxide Semiconductor Thin-Film Devices as Crosspoint-Type Synapse Elements and Working Confirmation of Letter Recognition.
Proceedings of the Neural Information Processing - 25th International Conference, 2018
Evaluation of Letter Reproduction System Using Cellular Neural Network and Oxide Semiconductor Synapses by Logic Simulation.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018
Proceedings of the IEEE Globecom Workshops, 2018
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
A Multi-Mode Error-Correction Solution Based on Split-Concatenation for Wireless Sensor Nodes.
J. Commun., 2017
Cellular neural network formed by simplified processing elements composed of thin-film transistors.
Neurocomputing, 2017
Neuromorphic Hardware Using Simplified Elements and Thin-Film Semiconductor Devices as Synapse Elements - Simulation of Hopfield and Cellular Neural Network -.
Proceedings of the Neural Information Processing - 24th International Conference, 2017
A Feasibility Study of Programmable Analog Calculation Unit for Approximate Computing.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Compression and Aggregation for Optimizing Information Transmission in Distributed CNN.
Proceedings of the Fifth International Symposium on Computing and Networking, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
2016
IEICE Trans. Inf. Syst., 2016
Simplification of Processing Elements in Cellular Neural Networks - Working Confirmation Using Circuit Simulation.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Letter Reproduction Simulator for Hardware Design of Cellular Neural Network Using Thin-Film Synapses - Crosspoint-Type Synapses and Simulation Algorithm.
Proceedings of the Neural Information Processing - 23rd International Conference, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the Fourth International Symposium on Computing and Networking, 2016
Proceedings of the 2016 IEEE Symposium in Low-Power and High-Speed Chips, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
Performance Evaluation of a 3D-Stencil Library for Distributed Memory Array Accelerators.
IEICE Trans. Inf. Syst., 2015
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Proceedings of the Third International Symposium on Computing and Networking, 2015
Proceedings of the Third International Symposium on Computing and Networking, 2015
Lowering the complexity of k-means clustering by BFS-dijkstra method for graph computing.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
IEEE Micro, 2014
A Tightly Coupled General Purpose Reconfigurable Accelerator LAPP and Its Power States for HotSpot-Based Energy Reduction.
IEICE Trans. Inf. Syst., 2014
Understanding Variations for Better Adjusting Parallel Supplemental Redundant Executions to Tolerate Timing Faults.
IEICE Trans. Inf. Syst., 2014
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
Proceedings of the Second International Symposium on Computing and Networking, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
A globally asynchronous locally synchronous DMR architecture for aggressive low-power fault toleration.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
A flexibly fault-tolerant FU array processor and its self-tuning scheme to locate permanently defective unit.
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
IEICE Trans. Inf. Syst., 2013
IEICE Trans. Inf. Syst., 2013
CAM Size Reduction Method for Auto-memorization Processor by Considering Characteristics of Loops.
Proceedings of the First International Symposium on Computing and Networking, 2013
Proceedings of the 2013 IEEE Symposium on Low-Power and High-Speed Chips, 2013
2012
RazorProtector: Maintaining Razor DVS Efficiency in Large IR-Drop Zones by an Adaptive Redundant Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
A Speed-up Technique for an Auto-Memoization Processor by Reusing Partial Results of Instruction Regions.
Proceedings of the Third International Conference on Networking and Computing, 2012
2011
An efficient conversion of quantum circuits to a linear nearest neighbor architecture.
Quantum Inf. Comput., 2011
IEICE Trans. Inf. Syst., 2011
A hybrid model of speculative execution and scout threading for auto-memoization processor.
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the Second International Conference on Networking and Computing, 2011
An efficient and reliable 1.5-way processor by fusion of space and time redundancies.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2011), 2011
2010
A Minimal Roll-Back Based Recovery Scheme for Fault Toleration in Pipeline Processors.
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010
A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations.
Proceedings of the First International Conference on Networking and Computing, 2010
2009
Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition.
Quantum Inf. Comput., 2009
Proceedings of the 2009 International Conference on Parallel and Distributed Computing, 2009
2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
2007
Design and evaluation of an auto-memoization processor.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads.
Proceedings of the Reconfigurable Computing: Architectures, 2007
2005
Program Phase Detection Based Dynamic Control Mechanisms for Pipeline Stage Unification Adoption.
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
2004
Implementation of Cell-Projection Parallel Volume Rendering with Dynamic Load Balancing.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2004
Simulating realistic force and shape of virtual cloth with adaptive meshes and its parallel implementation in OpenMP.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2004
Proceedings of the Grid Computing in Life Science, 2004
2001
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001
1995
Proceedings of the 9th international conference on Supercomputing, 1995