Yiyun Mao

Orcid: 0009-0008-4465-6809

According to our database¹, Yiyun Mao authored at least 3 papers between 2023 and 2025.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

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Bibliography

2025

An All-Digital Spread-Spectrum Clock Generator With Feedforward Gain Calibration for LPWAN Chirp Transmission System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, April, 2025

2023

Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2023

An ADPLL Design Model Based on LoRa IoT Application.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

Yiyun Mao

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