Yong-Jun Jo

According to our database, Yong-Jun Jo authored at least 6 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 65-nm 55.8-TOPS/W Compact 2T eDRAM-Based Compute-in-Memory Macro With Linear Calibration.

Xueyong Zhang, Yong-Jun Jo, Tony Tae-Hyoung Kim

IEEE Trans. Very Large Scale Integr. Syst., May, 2025

2024

Similarity-Aware Transposable SRAM Computation-In-Memory with Pulse-Based SAR ADC.

Yong-Jun Jo, Chufeng Yang, Yuanjin Zheng, Tony Tae-Hyoung Kim

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC.

Yong-Jun Jo, Boon Peng Yap, Dong-Hyun Yoon, Hyunjoon Kim, Yuanjin Zheng, Tony Tae-Hyoung Kim

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs.

Xin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023

2021

A 0.007 mm² 0.6 V 6 MS/s Low-Power Double Rail-to-Rail SAR ADC in 65-nm CMOS.

Yong-Jun Jo, Ju Eon Kim, Kwang-Hyun Baek, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. II Express Briefs, 2021

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing.

Vishal Sharma, Ju Eon Kim, Yong-Jun Jo, Yuzong Chen, Tony Tae-Hyoung Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021