Yong Sin Kim
Orcid: 0000-0002-6177-1496
According to our database1,
Yong Sin Kim
authored at least 29 papers
between 2003 and 2024.
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Bibliography
2024
Development and Analysis of an Origami-Based Elastomeric Actuator and Soft Gripper Control with Machine Learning and EMG Sensors.
Sensors, March, 2024
2023
2022
IEEE Access, 2022
16 x 10 Pressure Sensor CMOS Driver IC for Resistance Interfence Calibration of Cells.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
I-V Curve Tracer Based Intermittent Maximum Power Point Tracking for Photovoltaic System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
LDO Regulator Optimized on Power Efficiency and Load Transient Response with Voltage Damper and Body Loop Feedback.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Reliability and stability analysis and crack estimation of semiconductor gas sensors heater.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
Proceedings of the International Conference on Electronics, Information, and Communication, 2021
2020
On-Road Dynamic Pattern Projection Using an Active Mirror for Vehicle Warning Systems.
IEEE Trans. Veh. Technol., 2020
IEEE Access, 2020
IEEE Access, 2020
2019
A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Design of Road Surface Lighting System for Rear Lamp using Automotive Ultrasonic Sensor.
Proceedings of the International SoC Design Conference, 2018
2017
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Correlation-Based Optimal Chirp Rate Allocation for Chirp Spread Spectrum Using Multiple Linear Chirps.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Energy-Efficient Resource Allocation Strategy for Low Probability of Intercept and Anti-Jamming Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2014
A 2 GHz 130 mW Direct-Digital Frequency Synthesizer With a Nonlinear DAC in 55 nm CMOS.
IEEE J. Solid State Circuits, 2014
21.3 A 2GHz 130mW direct-digital frequency synthesizer with a nonlinear DAC in 55nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
IEEE Trans. Consumer Electron., 2013
IEEE Trans. Consumer Electron., 2013
Low-power pipelined phase accumulator using CMOS-CML hybrid F/Fs for pre-skewing operation.
IEICE Electron. Express, 2013
2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
2006
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
2005
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2003
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003