Woo-Seop Kim
Orcid: 0009-0008-6554-358X
According to our database1,
Woo-Seop Kim
authored at least 13 papers
between 2002 and 2023.
Collaborative distances:
Collaborative distances:
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Bibliography
2023
2013
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
2011
A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 31 ns Random Cycle VCAT-Based 4F <sup>2</sup> DRAM With Manufacturability and Enhanced Cell Efficiency.
IEEE J. Solid State Circuits, 2010
IEEE J. Solid State Circuits, 2010
2009
BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme.
IEEE J. Solid State Circuits, 2007
2006
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter.
IEEE J. Solid State Circuits, 2006
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
A 4-Gb/s/pin low-power memory I/O interface using 4-level simultaneous bi-directional signaling.
IEEE J. Solid State Circuits, 2005
A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.
IEEE J. Solid State Circuits, 2005
2002
A control network architecture based on EIA-709.1 protocol for power line data communications.
IEEE Trans. Consumer Electron., 2002