Yoshinobu Kaneda

Orcid: 0000-0002-2082-2023

According to our database1, Yoshinobu Kaneda authored at least 6 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.
IEEE J. Solid State Circuits, April, 2024

15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2022
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm<sup>2</sup> Density With Charge-Assisted Offset Cancellation Sense Amplifier.
IEEE J. Solid State Circuits, 2022

A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2019
A 65nm Silicon-on-Thin-Box (SOTB) Embedded 2T-MONOS Flash Achieving 0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019


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