Masaya Nakano
Orcid: 0000-0001-9509-6233
According to our database1,
Masaya Nakano authored at least 8 papers
between 2005 and 2025.
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Bibliography
2025
Imitation Learning for Robot Motions Based on Multimodal Foundation Model and Style Transformation.
IEEE Access, 2025
2024
Proceedings of the IEEE International Conference on Development and Learning, 2024
2022
A 40-nm Embedded SG-MONOS Flash Macro for High-End MCU Achieving 200-MHz Random Read Operation and 7.91-Mb/mm<sup>2</sup> Density With Charge-Assisted Offset Cancellation Sense Amplifier.
IEEE J. Solid State Circuits, 2022
2021
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2016
A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C.
IEEE J. Solid State Circuits, 2016
2015
7.3 A 28nm embedded SG-MONOS flash macro for automotive achieving 200MHz read operation and 2.0MB/S write throughput at Ti, of 170°C.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2005
Highly Flexible Row and Column Redundancy and Cycle Time Adaptive Read Data Path for Double Data Rate Synchronous Memories.
IEICE Trans. Electron., 2005