Koichi Takeda
This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.
Known people with the same name:
- Koichi Takeda 001 (Renesas Electronics, LSI Research Laboratory, Kawasaki, Japan)
- Koichi Takeda 002 (IBM Research, Tokyo, Japan)
- Koichi Takeda 003 (Nagoya University, Graduate School of Informatics, Japan)
- Koichi Takeda 004 (University of Tohoku, Department of Electrical and Communication Engineering, Sendai, Japan)
Bibliography
2024
A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.
IEEE J. Solid State Circuits, April, 2024
15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2021
A 40nm Embedded SG-MONOS Flash Macro for High-end MCU Achieving 200MHz Random Read Operation and 7.91Mb/mm2 Density with Charge Assisted Offset Cancellation Sense Amplifier.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2019
A 24MB Embedded Flash System Based on 28nm SG-MONOS Featuring 240MHz Read Operations and Robust Over-The-Air Software Update for Automotive.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2015
Proceedings of the Symposium on VLSI Circuits, 2015
2013
Investment Literacy and Individual Investor Biases: Survey Evidence in the Japanese Stock Market.
Rev. Socionetwork Strateg., 2013
2007
Proceedings of the Conference Record of the 2007 IEEE Industry Applications Conference Forty-Second IAS Annual Meeting, 2007
1996
IEEE J. Solid State Circuits, 1996
1995
A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors.
IEEE J. Solid State Circuits, November, 1995