Yoshinori Sakaue

According to our database, Yoshinori Sakaue authored at least 3 papers between 1989 and 1992.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1992

A 14-ns 14-Mb CMOS DRAM with 300-mW active power.

Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa

IEEE J. Solid State Circuits, September, 1992

A pulsed sensing scheme with a limited bit-line swing.

Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong

IEEE J. Solid State Circuits, April, 1992

1989

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing.

Nicky Chau-Chun Lu, Gary B. Bronner, Koji Kitamura, Roy E. Scheuerlein, Walter H. Henkels, Sang H. Dhong, Yasunao Katayama, Toshiaki Kirihata, Hideto Niijima, Robert L. Franch, Wei Wang, Motoo Nishiwaki, Frank L. Pesavento, T. V. Rajeevakumar, Yoshinori Sakaue, Yasusuke Suzuki, Yasunori Iguchi, Eiji Yano

IEEE J. Solid State Circuits, October, 1989