Toshiaki Kirihata

According to our database1, Toshiaki Kirihata authored at least 21 papers between 1995 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity.
IEEE J. Solid State Circuits, 2018

14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

2016
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access.
IEEE J. Solid State Circuits, 2016

Three-Dimensional Dynamic Random Access Memories Using Through-Silicon-Vias.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015
Oxygen vacancy traps in Hi-K/Metal gate technologies and their potential for embedded memory applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
Advanced memory topics.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.
IEEE J. Solid State Circuits, 2013

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM.
IEEE J. Solid State Circuits, 2013

Advanced memory topics.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
Dynamic intrinsic chip ID using 32nm high-K/metal gate SOI embedded DRAM.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache.
IEEE J. Solid State Circuits, 2011

Three Dimensional integration - Considerations for memory applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2009
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS.
IEEE J. Solid State Circuits, 2009

2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008

A Commercial Field-Programmable Dense eFUSE Array Memory with 99.999% Sense Yield for 45nm SOI CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.
Proceedings of the ESSCIRC 2008, 2008

2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

1997
Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1995
A low-noise TTL-compatible CMOS off-chip driver circuit.
IBM J. Res. Dev., 1995


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