Walter H. Henkels

According to our database, Walter H. Henkels authored at least 4 papers between 1980 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file.

Wei Hwang, Rajiv V. Joshi, Walter H. Henkels

IEEE J. Solid State Circuits, 1999

1997

A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit.

Wei Hwang, Rajiv V. Joshi, Walter H. Henkels

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1994

Large-signal 2T, 1C DRAM cell: signal and layout analysis.

Walter H. Henkels, Wei Hwang

IEEE J. Solid State Circuits, July, 1994

1980

Basic Design of a Josephson Technology Cache Memory.

S. M. Faris, Walter H. Henkels, E. A. Valsamakis, H. H. Zappe

IBM J. Res. Dev., 1980