Akashi Satoh

According to our database, Akashi Satoh authored at least 71 papers between 1997 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation.

Takaya Yoshitake, Akashi Satoh, Shinichiro Mito

Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022

Development of Hornet Detection Camera System for Smart Beekeeping.

Mitsuki Terada, Akashi Satoh

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2019

Fertilizer Management System for A Compact Hydroponic Planter.

Kaori Uehara, Hiromichi Ikeda, Akashi Satoh

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

2018

A Hydroponic Planter System to enable an Urban Agriculture Service Industry.

Akashi Satoh

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

2017

A compact hardware design of a sensor module for hydroponics.

Tomohiro Nishimura, Yuji Okuyama, Ayaka Matsushita, Hiromichi Ikeda, Akashi Satoh

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

Security evaluation of cryptographic modules against side-channel attack using a biased data set.

Masato Matsubayashi, Hendra Guntur, Akashi Satoh

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

2016

Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs.

Yu Nomata, Masato Matsubayashi, Kohei Sawada, Akashi Satoh

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

High-accuracy and low-cost sensor module for hydroponic culture system.

Tomohiro Nishimura, Yuji Okuyama, Akashi Satoh

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit.

Masato Matsubayashi, Akashi Satoh, Jun Ishii

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

GPGPU software implementation of authenticated encryption algorithm Minalpher.

Makiko Kosugi, Akashi Satoh

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

2015

Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card.

Masato Matsubayashi, Akashi Satoh

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

FPGA implementation of authenticated encryption algorithm Minalpher.

Makiko Kosug, Masahiro Yasuda, Akashi Satoh

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014

Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays.

Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara

J. Inf. Process., 2014

FPGA implementation of new standard hash function Keccak.

Tatsuya Honda, Hendra Guntur, Akashi Satoh

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Side-channel AttacK User Reference Architecture board SAKURA-G.

Hendra Guntur, Jun Ishii, Akashi Satoh

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2013

Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption.

Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh

IEICE Trans. Inf. Syst., 2013

A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.

Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

2012

Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates.

Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki

IEEE Trans. Very Large Scale Integr. Syst., 2012

Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current.

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue

IEICE Trans. Electron., 2012

A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments.

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

2011

Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEEE Trans. Very Large Scale Integr. Syst., 2011

An on-chip glitchy-clock generator for testing fault injection attacks.

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

J. Cryptogr. Eng., 2011

High-Performance Architecture for Concurrent Error Detection for AES Processors.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function.

Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.

Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh

Proceedings of the HOST 2011, 2011

2010

Comparative Power Analysis of Modular Exponentiation Algorithms.

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

IEEE Trans. Computers, 2010

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques.

Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Profiling attack using multivariate regression analysis.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

IEICE Electron. Express, 2010

Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.

Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

Hardware Implementations of Hash Function Luffa.

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the HOST 2010, 2010

Prototyping Platform for Performance Evaluation of SHA-3 Candidates.

Kazuyuki Kobayashi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, Leyla Nazhandali, Akashi Satoh

Proceedings of the HOST 2010, 2010

2009

High-Performance Hardware Architectures for Galois Counter Mode.

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

IEEE Trans. Computers, 2009

Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules.

Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh

Proceedings of the Information Security Applications, 10th International Workshop, 2009

Is the differential frequency-based attack effective against random delay insertion?

Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

Compact and High-speed Hardware Architectures for Hash Function Tiger.

Akashi Satoh, Nicolas Sklavos

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Differential power analysis of AES ASIC implementations with various S-box circuits.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

Development of side-channel attack standard evaluation environment.

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.

Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2009

2008

A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks.

Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the Information Security Applications, 9th International Workshop, 2008

Enhanced Correlation Power Analysis Using Key Screening Technique.

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems.

Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda

Proceedings of the Advances in Information and Computer Security, 2008

High-performance ASIC implementations of the 128-bit block cipher CLEFIA.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ASIC hardware implementations for 512-bit hash function Whirlpool.

Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Enhanced power analysis attack using chosen message against RSA hardware implementations.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Systematic design of high-radix Montgomery multipliers for RSA processors.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the 26th International Conference on Computer Design, 2008

Chosen-message SPA attacks against FPGA-based RSA hardware implementations.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the FPL 2008, 2008

Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems.

Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda

Proceedings of the FPL 2008, 2008

High-Performance Concurrent Error Detection Scheme for AES Hardware.

Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki

Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs.

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

Proceedings of the Cryptographic Hardware and Embedded Systems, 2008

2007

ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS.

Akashi Satoh, Tadanobu Inoue

Integr., 2007

High-Speed Pipelined Hardware Architecture for Galois Counter Mode.

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

Proceedings of the Information Security, 10th International Conference, 2007

A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128.

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-Speed Parallel Hardware Architecture for Galois Counter Mode.

Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure.

Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier.

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

High-speed hardware architectures for authenticated encryption mode GCM.

Akashi Satoh

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching.

Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005

Hardware Architecture and Cost Estimates for Breaking SHA-1.

Akashi Satoh

Proceedings of the Information Security, 8th International Conference, 2005

2004

A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture.

Sumio Morioka, Akashi Satoh

IEEE Trans. Very Large Scale Integr. Syst., 2004

On-demand design service innovations.

Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara

IBM J. Res. Dev., 2004

2003

A Scalable Dual-Field Elliptic Curve Cryptographic Processor.

Akashi Satoh, Kohji Takano

IEEE Trans. Computers, 2003

Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES.

Akashi Satoh, Sumio Morioka

Proceedings of the Information Security, 6th International Conference, 2003

Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia.

Akashi Satoh, Sumio Morioka

Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002

Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI.

Akashi Satoh, Sumio Morioka

Proceedings of the Information Security, 5th International Conference, 2002

An Optimized S-Box Circuit Architecture for Low Power AES Design.

Sumio Morioka, Akashi Satoh

Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

2001

A Compact Rijndael Hardware Architecture with S-Box Optimization.

Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh

Proceedings of the Advances in Cryptology, 2001

2000

High-Speed MARS Hardware.

Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon

Proceedings of the Third Advanced Encryption Standard Candidate Conference, 2000

1997

A High-Speed Small RSA Encryption LSI with Low Power Dissipation.

Akashi Satoh, Yoshinao Kobayashi, Hideto Niijima, Nobuyuki Ooba, Seiji Munetoh, Sadamichi Sone

Proceedings of the Information Security, First International Workshop, 1997

Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip.

W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997