Youbean Kim

Orcid: 0009-0008-3317-9859

According to our database1, Youbean Kim authored at least 9 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Low Loss Hybrid-Plane PCB Structure for Improving Signal Quality in High-Speed Signal Transmission.
IEEE Access, 2024

2010
Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method.
IEICE Trans. Inf. Syst., 2010

2008
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.
IEICE Trans. Inf. Syst., 2008

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters.
IEICE Trans. Electron., 2008

A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals.
IEICE Trans. Electron., 2008

2007
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing.
IET Comput. Digit. Tech., 2007

A New Analog-to-Digital Converter BIST Considering a Transient Zone.
IEICE Trans. Electron., 2007

2006
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure.
Proceedings of the 15th Asian Test Symposium, 2006

2005
A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005


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