Sungho Kang

According to our database1, Sungho Kang authored at least 113 papers between 1981 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Machine Learning based Scan Chain Diagnosis for Double Faults.
Proceedings of the 20th International SoC Design Conference, 2023

A New Flip-flop Shared Architecture of Test Point Insertion for Scan Design.
Proceedings of the 20th International SoC Design Conference, 2023

2022
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST.
Proceedings of the 19th International SoC Design Conference, 2022

Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset.
Proceedings of the 19th International SoC Design Conference, 2022

Logic Diagnosis Based on Deep Learning for Multiple Faults.
Proceedings of the 19th International SoC Design Conference, 2022

Pair-Grouping Scan Chain Architecture for Multiple Scan Cell Fault Diagnosis.
Proceedings of the 19th International SoC Design Conference, 2022

2021
Hybrid Test Access Mechanism for Multiple Identical Cores.
Proceedings of the 18th International SoC Design Conference, 2021

Secure Scan Design through Pseudo Fault Injection.
Proceedings of the 18th International SoC Design Conference, 2021

Long-lasting Leaf Water Stress Detector Based On An Infrared Micromechanical Photoswitch And A Solar Powered Sunlight Digitizer.
Proceedings of the 2021 IEEE Sensors, Sydney, Australia, October 31 - Nov. 3, 2021, 2021

2020
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.
Sensors, 2020

Analysis of Electroencephalography Signals on the Contents of Cognitive Function Game: Attention and Memory.
J. Medical Imaging Health Informatics, 2020

Diagnosis of Scan Chain Faults Based-on Machine-Learning.
Proceedings of the International SoC Design Conference, 2020

2019
A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology.
Proceedings of the 2019 International SoC Design Conference, 2019

Zero-Power Chemical Sensor Based on a Polymer/Metal Micromechanical Switch.
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019

2018
Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU.
Proceedings of the TENCON 2018, 2018

A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain.
Proceedings of the International SoC Design Conference, 2018

2-D Failure Bitmap Compression Using Line Fault Marking Method.
Proceedings of the International SoC Design Conference, 2018

A Test Methodology for Neural Computing Unit.
Proceedings of the International SoC Design Conference, 2018

A False Alarm-Free Zero-Power Micromechanical Photoswitch.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

Spectroscopic Chemical Sensing Based on Narrowband MEMS Resonant Infrared Detectors.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

2017
R<sup>2</sup>-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies.
IEEE Trans. Reliab., 2017

Test item priority estimation for high parallel test efficiency under ATE debug time constraints.
Proceedings of the International Test Conference in Asia, 2017

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Broadcast scan compression based on deterministic pattern generation algorithm.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

LARECD: Low area overhead and reliable error correction DMR architecture.
Proceedings of the International SoC Design Conference, 2017

Test data reduction method based on berlekamp-massey algorithm.
Proceedings of the International SoC Design Conference, 2017

An efficient built-in self-repair scheme for area reduction.
Proceedings of the International SoC Design Conference, 2017

Threshold scaling of near-zero power micromechanical photoswitches using bias voltage.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017

2016
Optimized Built-In Self-Repair for Multiple Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Survey of Repair Analysis Algorithms for Memories.
ACM Comput. Surv., 2016

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs.
Proceedings of the International SoC Design Conference, 2016

P-backtracking: A new scan chain diagnosis method with probability.
Proceedings of the International SoC Design Conference, 2016

A test methodology to screen scan-path failures.
Proceedings of the International SoC Design Conference, 2016

Software-based embedded core test using multi-polynomial for test data reduction.
Proceedings of the International SoC Design Conference, 2016

Narrowband MEMS resonant infrared detectors based on ultrathin perfect plasmonic absorbers.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

2015
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.
IEEE Trans. Reliab., 2015

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency.
Sensors, 2015

Reduced-code test method using sub-histograms for pipelined ADCs.
IEICE Electron. Express, 2015

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv., 2015

Near optimal repair rate built-in redundancy analysis with very small hardware overhead.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2014
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Recovery-enhancing task scheduling for multicore processors under NBTI impact.
IEICE Electron. Express, 2014

A novel test access mechanism for parallel testing of multi-core system.
IEICE Electron. Express, 2014

2013
Built-In Self-Test for Static ADC Testing with a Triangle-Wave.
IEICE Trans. Electron., 2013

Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter.
IEICE Trans. Commun., 2013

Dynamic thermal management for 3D multicore processors under process variations.
IEICE Electron. Express, 2013

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express, 2013

Bit transmission error correction scheme for FlexRay based automotive communication systems.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
An accurate diagnosis of transition fault clusters based on single fault simulation.
IEICE Electron. Express, 2012

A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm.
IEICE Electron. Express, 2012

An efficient IP address lookup algorithm based on a small balanced tree using entry reduction.
Comput. Networks, 2012

Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012

2011
Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach.
IEICE Trans. Electron., 2011

An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector.
IEICE Trans. Commun., 2011

Path search engine for fast optimal path search using efficient hardware architecture.
Proceedings of the International SoC Design Conference, 2011

New Fault Detection Algorithm for Multi-level Cell Flash Memroies.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method.
IEICE Trans. Inf. Syst., 2010

2009
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2009

ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Effective Programmable Memory BIST for Embedded Memory.
IEICE Trans. Inf. Syst., 2009

An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search.
Proceedings of the Communication and Networking, 2009

2008
MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.
IEICE Trans. Inf. Syst., 2008

A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.
IEICE Trans. Inf. Syst., 2008

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters.
IEICE Trans. Electron., 2008

A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals.
IEICE Trans. Electron., 2008

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Prevenient Voltage Stress Test Method for High Density Memory.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A new low energy BIST using a statistical code.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing.
IET Comput. Digit. Tech., 2007

A New Analog-to-Digital Converter BIST Considering a Transient Zone.
IEICE Trans. Electron., 2007

2006
A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets.
IEICE Trans. Inf. Syst., 2006

Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments.
Proceedings of the Ubiquitous Convergence Technology, First International Conference, 2006

SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.
Proceedings of the Computational Intelligence, 2006

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure.
Proceedings of the 15th Asian Test Symposium, 2006

2005
A New Low Power Test Pattern Generator for BIST Architecture.
IEICE Trans. Electron., 2005

An Effective Built-In Self-Test for Chargepump PLL.
IEICE Trans. Electron., 2005

Increasing Embedding Probabilities of RPRPs in RIN Based BIST.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Code-width testing-based compact ADC BIST circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

New distributed arithmetic algorithm for low-power FIR filter implementation.
IEEE Signal Process. Lett., 2004

An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004

Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm.
Proceedings of the Information Networking, 2004

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem.
Simul., 2003

2002
A New DSP Architecture for Correcting Errors Using Viterbi Algorithm.
Proceedings of the Advanced Internet Services and Applications, 2002

An Efficient On-Line Monitoring BIST for Remote Service System.
Proceedings of the Advanced Internet Services and Applications, 2002

A New Survival Architecture for Network Processors.
Proceedings of the Advanced Internet Services and Applications, 2002

2001
A simple, scalable, and stable explicit rate allocation algorithm for MAX-MIN flow control with minimum rate guarantee.
IEEE/ACM Trans. Netw., 2001

Control-theoretic max-min flow control with minimum rate guarantee.
Proceedings of the Global Telecommunications Conference, 2001

1999
A New Weight Set Generation Algorithm for Weighted Random Pattern Generation.
Proceedings of the IEEE International Conference On Computer Design, 1999

1997
Built-in Self Test for Contect Addressable Memories.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture.
VLSI Design, 1996

Efficient Simulation Model Generation Using Automatic Programming Techniques.
Proceedings of the 28th conference on Winter simulation, 1996

1995
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994
The simulation automation system (SAS); concepts, implementation, and results.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Automatic Simulator Generation System.
Simul., 1994

Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.
IEEE Des. Test Comput., 1994

Fastpath: A Path-Delay Test Generator for Standard Scan Designs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Path-Delay Fault Simulation for a Standard Scan Design Methodology.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Automatic VHDL Model Generation System.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Modeling and Simulation of Design Errors.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

New design error modeling and metrics for design validation.
Proceedings of the conference on European design automation, 1992

1983
Linear ordering and application to placement.
Proceedings of the 20th Design Automation Conference, 1983

1981
Automatic PLA synthesis from a DDL-P description.
Proceedings of the 18th Design Automation Conference, 1981


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