Sungho Kang
According to our database1,
Sungho Kang
authored at least 113 papers
between 1981 and 2023.
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Bibliography
2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
2022
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST.
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
Proceedings of the 19th International SoC Design Conference, 2022
2021
Proceedings of the 18th International SoC Design Conference, 2021
Proceedings of the 18th International SoC Design Conference, 2021
Long-lasting Leaf Water Stress Detector Based On An Infrared Micromechanical Photoswitch And A Solar Powered Sunlight Digitizer.
Proceedings of the 2021 IEEE Sensors, Sydney, Australia, October 31 - Nov. 3, 2021, 2021
2020
Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.
Sensors, 2020
Analysis of Electroencephalography Signals on the Contents of Cognitive Function Game: Attention and Memory.
J. Medical Imaging Health Informatics, 2020
Proceedings of the International SoC Design Conference, 2020
2019
Proceedings of the 2019 International SoC Design Conference, 2019
Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019
2018
Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU.
Proceedings of the TENCON 2018, 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the International SoC Design Conference, 2018
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018
2017
R<sup>2</sup>-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies.
IEEE Trans. Reliab., 2017
Test item priority estimation for high parallel test efficiency under ATE debug time constraints.
Proceedings of the International Test Conference in Asia, 2017
Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Threshold scaling of near-zero power micromechanical photoswitches using bias voltage.
Proceedings of the 2017 IEEE SENSORS, Glasgow, United Kingdom, October 29, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Proceedings of the International SoC Design Conference, 2016
Narrowband MEMS resonant infrared detectors based on ultrathin perfect plasmonic absorbers.
Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016
2015
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.
IEEE Trans. Reliab., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Sensors, 2015
IEICE Electron. Express, 2015
Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv., 2015
Near optimal repair rate built-in redundancy analysis with very small hardware overhead.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
2014
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2014
A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEICE Electron. Express, 2014
IEICE Electron. Express, 2014
2013
IEICE Trans. Electron., 2013
IEICE Trans. Commun., 2013
IEICE Electron. Express, 2013
Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express, 2013
Bit transmission error correction scheme for FlexRay based automotive communication systems.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories.
Proceedings of the 22nd Asian Test Symposium, 2013
2012
IEICE Electron. Express, 2012
A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm.
IEICE Electron. Express, 2012
An efficient IP address lookup algorithm based on a small balanced tree using entry reduction.
Comput. Networks, 2012
Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012
2011
IEICE Trans. Electron., 2011
An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector.
IEICE Trans. Commun., 2011
Path search engine for fast optimal path search using efficient hardware architecture.
Proceedings of the International SoC Design Conference, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEICE Trans. Inf. Syst., 2010
2009
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEICE Trans. Inf. Syst., 2009
An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009
Proceedings of the Communication and Networking, 2009
2008
MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.
IEICE Trans. Inf. Syst., 2008
A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.
IEICE Trans. Inf. Syst., 2008
IEICE Trans. Electron., 2008
A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals.
IEICE Trans. Electron., 2008
A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method.
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing.
IET Comput. Digit. Tech., 2007
IEICE Trans. Electron., 2007
2006
IEICE Trans. Inf. Syst., 2006
Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments.
Proceedings of the Ubiquitous Convergence Technology, First International Conference, 2006
Proceedings of the Computational Intelligence, 2006
TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure.
Proceedings of the 15th Asian Test Symposium, 2006
2005
IEICE Trans. Electron., 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
IEEE Signal Process. Lett., 2004
An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004
Proceedings of the Information Networking, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Simul., 2003
2002
Proceedings of the Advanced Internet Services and Applications, 2002
Proceedings of the Advanced Internet Services and Applications, 2002
Proceedings of the Advanced Internet Services and Applications, 2002
2001
A simple, scalable, and stable explicit rate allocation algorithm for MAX-MIN flow control with minimum rate guarantee.
IEEE/ACM Trans. Netw., 2001
Proceedings of the Global Telecommunications Conference, 2001
1999
Proceedings of the IEEE International Conference On Computer Design, 1999
1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
1996
A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture.
VLSI Design, 1996
Proceedings of the 28th conference on Winter simulation, 1996
1995
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.
IEEE Des. Test Comput., 1994
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994
1993
Automatic VHDL Model Generation System.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992
Proceedings of the conference on European design automation, 1992
1983
Proceedings of the 20th Design Automation Conference, 1983
1981
Proceedings of the 18th Design Automation Conference, 1981