Sungho Kang

According to our database1, Sungho Kang authored at least 193 papers between 1981 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2021
Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs.
IEEE Trans. Very Large Scale Integr. Syst., 2021

A Secure Scan Architecture Protecting Scan Test and Scan Dump Using Skew-Based Lock and Key.
IEEE Access, 2021

An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process.
IEEE Access, 2021

On-Chip Error Detection Reusing Built-In Self-Repair for Silicon Debug.
IEEE Access, 2021

A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs.
IEEE Access, 2021

Reconfigurable Scan Architecture for High Diagnostic Resolution.
IEEE Access, 2021

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory.
IEEE Access, 2021

2020
GPU-Based Redundancy Analysis Using Concurrent Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2020

A New Logic Topology-Based Scan Chain Stitching for Test-Power Reduction.
IEEE Trans. Circuits Syst., 2020

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

A 3-D Rotation-Based Through-Silicon via Redundancy Architecture for Clustering Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor Networks.
Sensors, 2020

Analysis of Electroencephalography Signals on the Contents of Cognitive Function Game: Attention and Memory.
J. Medical Imaging Health Informatics, 2020

Fine-Grained Defect Diagnosis for CMOL FPGA Circuits.
IEEE Access, 2020

Fail Memory Configuration Set for RA Estimation.
Proceedings of the IEEE International Test Conference, 2020

W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction.
Proceedings of the IEEE International Test Conference in Asia, 2020

Diagnosis of Scan Chain Faults Based-on Machine-Learning.
Proceedings of the International SoC Design Conference, 2020

Redundancy Analysis Optimization with Clustered Known Solutions for High Speed Repair.
Proceedings of the International SoC Design Conference, 2020

Memory-like Defect Diagnosis for CMOL FPGAs.
Proceedings of the International SoC Design Conference, 2020

2019
Dynamic Built-In Redundancy Analysis for Memory Repair.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Test-Friendly Data-Selectable Self-Gating (DSSG).
IEEE Trans. Very Large Scale Integr. Syst., 2019

Highly Reliable Redundant TSV Architecture for Clustered Faults.
IEEE Trans. Reliab., 2019

TSV Repair Architecture for Clustered Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

An Efficient BIRA Utilizing Characteristics of Spare Pivot Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Tunable Compact Probing Detector with Fast Analysis Time Against Invasive Attacks.
Proceedings of the 2019 International SoC Design Conference, 2019

Redundancy Analysis based on Fault Distribution for Memory with Complex Spares.
Proceedings of the 2019 International SoC Design Conference, 2019

Transition-delay Test Methodology for Designs with Self-gating.
Proceedings of the 2019 International SoC Design Conference, 2019

A New Scan Chain Reordering Method for Low Power Consumption based on Care Bit Density.
Proceedings of the 2019 International SoC Design Conference, 2019

A Hardware-efficient TSV Repair Scheme Based on Butterfly Topology.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
An Area-Efficient BIRA With 1-D Spare Segments.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Fast Built-In Redundancy Analysis Based on Sequential Spare Line Allocation.
IEEE Trans. Reliab., 2018

Thermal Aware Test Scheduling for NTV Circuit.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Fault Group Pattern Matching With Efficient Early Termination for High-Speed Redundancy Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Test Resource Reused Debug Scheme to Reduce the Post-Silicon Debug Cost.
IEEE Trans. Computers, 2018

A Statistic-Based Scan Chain Reordering for Energy-Quality Scalable Scan Test.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Neural Network Reliability Enhancement Approach Using Dropout Underutilization in GPU.
Proceedings of the TENCON 2018, 2018

3D Memory Formed of Unrepairable Memory Dice and Spare Layer.
Proceedings of the TENCON 2018, 2018

Dynamic voltage Drop induced Path Delay Analysis for STV and NTV Circuits during At-speed Scan Test.
Proceedings of the International SoC Design Conference, 2018

A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain.
Proceedings of the International SoC Design Conference, 2018

Low Power Scan Chain Architecture Based on Circuit Topology.
Proceedings of the International SoC Design Conference, 2018

2-D Failure Bitmap Compression Using Line Fault Marking Method.
Proceedings of the International SoC Design Conference, 2018

A Test Methodology for Neural Computing Unit.
Proceedings of the International SoC Design Conference, 2018

2017
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Chain-Based Approach for Fast Through-Silicon-Via Coupling Delay Estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2017

R<sup>2</sup>-TSV: A Repairable and Reliable TSV Set Structure Reutilizing Redundancies.
IEEE Trans. Reliab., 2017

FRESH: A New Test Result Extraction Scheme for Fast TSV Tests.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

An On-Chip Error Detection Method to Reduce the Post-Silicon Debug Time.
IEEE Trans. Computers, 2017

DRAM-Based Error Detection Method to Reduce the Post-Silicon Debug Time for Multiple Identical Cores.
IEEE Trans. Computers, 2017

Proof of Concept of Home IoT Connected Vehicles.
Sensors, 2017

Reconfigurable scan architecture for test power and data volume reduction.
IEICE Electron. Express, 2017

A novel X-filling method for capture power reduction.
IEICE Electron. Express, 2017

Test item priority estimation for high parallel test efficiency under ATE debug time constraints.
Proceedings of the International Test Conference in Asia, 2017

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Broadcast scan compression based on deterministic pattern generation algorithm.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

A selective error data capture method using on-chip DRAM for silicon debug of multi-core design.
Proceedings of the International SoC Design Conference, 2017

LARECD: Low area overhead and reliable error correction DMR architecture.
Proceedings of the International SoC Design Conference, 2017

Test data reduction method based on berlekamp-massey algorithm.
Proceedings of the International SoC Design Conference, 2017

A new repair scheme for TSV-based 3D memory using base die repair cells.
Proceedings of the International SoC Design Conference, 2017

An efficient built-in self-repair scheme for area reduction.
Proceedings of the International SoC Design Conference, 2017

2016
Optimized Built-In Self-Repair for Multiple Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A New 3-D Fuse Architecture to Improve Yield of 3-D Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Survey of Repair Analysis Algorithms for Memories.
ACM Comput. Surv., 2016

A TSV test structure for simultaneously detecting resistive open and bridge defects in 3D-ICs.
Proceedings of the International SoC Design Conference, 2016

P-backtracking: A new scan chain diagnosis method with probability.
Proceedings of the International SoC Design Conference, 2016

A test methodology to screen scan-path failures.
Proceedings of the International SoC Design Conference, 2016

Process variation-aware bridge fault analysis.
Proceedings of the International SoC Design Conference, 2016

Software-based embedded core test using multi-polynomial for test data reduction.
Proceedings of the International SoC Design Conference, 2016

Discussion of cost-effective redundancy architectures.
Proceedings of the International SoC Design Conference, 2016

A new online test and debug methodology for automotive camera image processing system.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Test access mechaism for stack test time reduction of 3-dimensional integrated circuit.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability.
IEEE Trans. Reliab., 2015

A 3 Dimensional Built-In Self-Repair Scheme for Yield Improvement of 3 Dimensional Memories.
IEEE Trans. Reliab., 2015

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Eco Assist Techniques through Real-time Monitoring of BEV Energy Usage Efficiency.
Sensors, 2015

Reduced-code test method using sub-histograms for pipelined ADCs.
IEICE Electron. Express, 2015

Lifetime Reliability Enhancement of Microprocessors: Mitigating the Impact of Negative Bias Temperature Instability.
ACM Comput. Surv., 2015

A scan shifting method based on clock gating of multiple groups for low power scan testing.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Low power scan bypass technique with test data reduction.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Near optimal repair rate built-in redundancy analysis with very small hardware overhead.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
A Delay Test Architecture for TSV With Resistive Open Defects in 3-D Stacked Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Interleaving Test Algorithm for Subthreshold Leakage-Current Defects in DRAM Considering the Equal Bit Line Stress.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2014

A New Fuse Architecture and a New Post-Share Redundancy Scheme for Yield Enhancement in 3-D-Stacked Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Recovery-enhancing task scheduling for multicore processors under NBTI impact.
IEICE Electron. Express, 2014

A novel test access mechanism for parallel testing of multi-core system.
IEICE Electron. Express, 2014

A Scalable and Parallel Test Access Strategy for NoC-Based Multicore System.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Built-In Self-Test for Static ADC Testing with a Triangle-Wave.
IEICE Trans. Electron., 2013

Acceleration of Deep Packet Inspection Using a Multi-Byte Processing Prefilter.
IEICE Trans. Commun., 2013

Dynamic thermal management for 3D multicore processors under process variations.
IEICE Electron. Express, 2013

Thermal-aware dynamic voltage frequency scaling for many-core processors under process variations.
IEICE Electron. Express, 2013

Bit transmission error correction scheme for FlexRay based automotive communication systems.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

A Die Selection and Matching Method with Two Stages for Yield Enhancement of 3-D Memories.
Proceedings of the 22nd Asian Test Symposium, 2013

2012
An accurate diagnosis of transition fault clusters based on single fault simulation.
IEICE Electron. Express, 2012

A method for the fast diagnosis of multiple defects using an efficient candidate selection algorithm.
IEICE Electron. Express, 2012

An efficient IP address lookup algorithm based on a small balanced tree using entry reduction.
Comput. Networks, 2012

Integration of dual channel timing formatter system for high speed memory test equipment.
Proceedings of the International SoC Design Conference, 2012

2011
A Memory-Efficient Bit-Split Parallel String Matching Using Pattern Dividing for Intrusion Detection Systems.
IEEE Trans. Parallel Distributed Syst., 2011

A Lossless Color Image Compression Architecture Using a Parallel Golomb-Rice Hardware CODEC.
IEEE Trans. Circuits Syst. Video Technol., 2011

Communication-aware task scheduling and voltage selection for total energy minimization in a multiprocessor system using Ant Colony Optimization.
Inf. Sci., 2011

Noise-Tolerant DAC BIST Scheme Using Integral Calculus Approach.
IEICE Trans. Electron., 2011

An Efficient IP Address Lookup Scheme Using Balanced Binary Search with Minimal Entry and Optimal Prefix Vector.
IEICE Trans. Commun., 2011

Path search engine for fast optimal path search using efficient hardware architecture.
Proceedings of the International SoC Design Conference, 2011

New Fault Detection Algorithm for Multi-level Cell Flash Memroies.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
EOF: Efficient Built-In Redundancy Analysis Methodology With Optimal Repair Rate.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Advanced BIRA for Memories With an Optimal Repair Rate and Fast Analysis Speed by Using a Branch Analyzer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

A Fast IP Address Lookup Algorithm Based on Search Space Reduction.
IEICE Trans. Commun., 2010

Selective Scan Slice Grouping Technique for Efficient Test Data Compression.
IEICE Trans. Inf. Syst., 2010

A Selective Scan Chain Activation Technique for Minimizing Average and Peak Power Consumption.
IEICE Trans. Inf. Syst., 2010

A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection.
IEICE Trans. Commun., 2010

Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method.
IEICE Trans. Inf. Syst., 2010

A Pattern Partitioning Algorithm for Memory-Efficient Parallel String Matching in Deep Packet Inspection.
IEICE Trans. Commun., 2010

A Hardware-Efficient Pattern Matching Architecture Using Process Element Tree for Deep Packet Inspection.
IEICE Trans. Commun., 2010

A high performance network-on-chip scheme using lossless data compression.
IEICE Electron. Express, 2010

A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection.
IEICE Electron. Express, 2010

A Pattern Group Partitioning for Parallel String Matching using a Pattern Grouping Metric.
IEEE Commun. Lett., 2010

2009
A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2009

ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Effective Programmable Memory BIST for Embedded Memory.
IEICE Trans. Inf. Syst., 2009

Grouped Scan Slice Repetition Method for Reducing Test Data Volume and Test Application Time.
IEICE Trans. Inf. Syst., 2009

Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume.
IEICE Electron. Express, 2009

A memory-efficient parallel string matching for intrusion detection systems.
IEEE Commun. Lett., 2009

A High-Level Signal Integrity Fault Model and Test Methodology for Long On-Chip Interconnections.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

FPGA-based verification methodology of SoC-type CMOS image signal processor.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

An Efficient Hardware Architecture of the A-star Algorithm for the Shortest Path Search Engine.
Proceedings of the International Conference on Networked Computing and Advanced Information Management, 2009

An Ant Colony Optimization Approach for the Preference-Based Shortest Path Search.
Proceedings of the Communication and Networking, 2009

2008
Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

MTR-Fill: A Simulated Annealing-Based X-Filling Technique to Reduce Test Power Dissipation for Scan-Based Designs.
IEICE Trans. Inf. Syst., 2008

A New Scan Power Reduction Scheme Using Transition Freezing for Pseudo-Random Logic BIST.
IEICE Trans. Inf. Syst., 2008

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters.
IEICE Trans. Electron., 2008

A New Built-in Self Test Scheme for Phase-Locked Loops Using Internal Digital Signals.
IEICE Trans. Electron., 2008

Ant colony based efficient triplet calculation methodology for arithmetic built-in self test.
IEICE Electron. Express, 2008

An Effective Power Reduction Methodology for Deterministic BIST Using Auxiliary LFSR.
J. Electron. Test., 2008

A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.
J. Electron. Test., 2008

An Efficient Scan Chain Diagnosis Method Using a New Symbolic Simulation.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method.
Proceedings of the 2008 IEEE International Test Conference, 2008

A Prevenient Voltage Stress Test Method for High Density Memory.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

An Effective Hybrid Test Data Compression Method Using Scan Chain Compaction and Dictionary-Based Scheme.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

XPDF-ATPG: An Efficient Test Pattern Generation for Crosstalk-Induced Faults.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

A new low energy BIST using a statistical code.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing.
IET Comput. Digit. Tech., 2007

A New Analog-to-Digital Converter BIST Considering a Transient Zone.
IEICE Trans. Electron., 2007

MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs.
J. Electron. Test., 2007

2006
MICRO: a new hybrid test data compression/decompression scheme.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Increasing encoding efficiency of LFSR reseeding-based test compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Clustered RIN BIST Based on Signal Probabilities of Deterministic Test Sets.
IEICE Trans. Inf. Syst., 2006

An Efficient Dictionary Organization for Maximum Diagnosis.
J. Electron. Test., 2006

Improved Reinforcement Computing to Implement AntNet-Based Routing Using General NPs for Ubiquitous Environments.
Proceedings of the Ubiquitous Convergence Technology, First International Conference, 2006

System on a Chip Implementation of Social Insect Behavior for Adaptive Network Routing.
Proceedings of the Computational Intelligence, 2006

SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.
Proceedings of the Computational Intelligence, 2006

2005
A New Low Power Test Pattern Generator for BIST Architecture.
IEICE Trans. Electron., 2005

An Effective Built-In Self-Test for Chargepump PLL.
IEICE Trans. Electron., 2005

A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Increasing Embedding Probabilities of RPRPs in RIN Based BIST.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
A new maximal diagnosis algorithm for interconnect test.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Code-width testing-based compact ADC BIST circuit.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

New distributed arithmetic algorithm for low-power FIR filter implementation.
IEEE Signal Process. Lett., 2004

An Acceleration Processor for Data Intensive Scientific Computing.
IEICE Trans. Inf. Syst., 2004

An In-Order SMT Architecture with Static Resource Partitioning for Consumer Applications.
Proceedings of the Parallel and Distributed Computing: Applications and Technologies, 2004

Route Reinforcement for Efficient QoS Routing Based on Ant Algorithm.
Proceedings of the Information Networking, 2004

RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Test-decompression mechanism using a variable-length multiple-polynomial LFSR.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Accurate Logic Simulation by Overcoming the Unknown Value Propagation Problem.
Simul., 2003

A New Maximal Diagnosis Algorithm for Bus-structured Systems.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002
DPSC SRAM Transparent Test Algorithm.
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A New DSP Architecture for Correcting Errors Using Viterbi Algorithm.
Proceedings of the Advanced Internet Services and Applications, 2002

An Efficient On-Line Monitoring BIST for Remote Service System.
Proceedings of the Advanced Internet Services and Applications, 2002

A New Survival Architecture for Network Processors.
Proceedings of the Advanced Internet Services and Applications, 2002

2001
A simple, scalable, and stable explicit rate allocation algorithm for MAX-MIN flow control with minimum rate guarantee.
IEEE/ACM Trans. Netw., 2001

A new multiple weight set calculation algorithm.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A Heuristic for Multiple Weight Set Generation.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Control-theoretic max-min flow control with minimum rate guarantee.
Proceedings of the Global Telecommunications Conference, 2001

1999
A New Weight Set Generation Algorithm for Weighted Random Pattern Generation.
Proceedings of the IEEE International Conference On Computer Design, 1999

An Efficient Interconnect Test Using BIST Module in a Boundary-Scan Environment.
Proceedings of the IEEE International Conference On Computer Design, 1999

At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks.
Proceedings of the 1999 Design, 1999

1997
Built-in Self Test for Contect Addressable Memories.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996
Efficient Simulation Model Generation Using Automatic Programming Techniques.
Proceedings of the 28th conference on Winter simulation, 1996

1995
Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation.
Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture (HPCA 1995), 1995

1994
The simulation automation system (SAS); concepts, implementation, and results.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Automatic Simulator Generation System.
Simul., 1994

Design Validation: Comparing Theoretical and Empirical Results of Design Error Modeling.
IEEE Des. Test Comput., 1994

Fastpath: A Path-Delay Test Generator for Standard Scan Designs.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

Path-Delay Fault Simulation for a Standard Scan Design Methodology.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1993
Automatic VHDL Model Generation System.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993

1992
Modeling and Simulation of Design Errors.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

New design error modeling and metrics for design validation.
Proceedings of the conference on European design automation, 1992

1983
Linear ordering and application to placement.
Proceedings of the 20th Design Automation Conference, 1983

1981
Automatic PLA synthesis from a DDL-P description.
Proceedings of the 18th Design Automation Conference, 1981


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