Yu Liu

According to our database, Yu Liu authored at least 5 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2026

A 12-bit 10 GS/s Pre-Sampling Pipelined ADC With Split-Capacitor-Based Parasitic Compensation Technique.

Yu Liu, Mingliang Chen, Yupeng Shen, Yao Yang, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu

IEEE Trans. Circuits Syst. II Express Briefs, April, 2026

2025

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC.

Yu Liu, Yupeng Shen, Mingliang Chen, Hui Xu, Xubin Chen, Jiarui Liu, Zhiyu Wang, Faxin Yu

IEEE Trans. Very Large Scale Integr. Syst., January, 2025

A low-fractional-spur fractional-N PLL using a probability-distribution-shaping delta-sigma modulator.

Yao Yang, Faxin Yu, Haoming Li, Jiahao Chen, Tengjia Wang, Yu Liu, Hua Chen, Jiarui Liu

IEICE Electron. Express, 2025

2024

A new extraction method of GaN switch-HEMT small-signal model with capacitance scanning algorithm.

Jiashun Lang, Beibei Lv, Di Zhang, Yu Liu, Pengfei Zhang, Jiongjiong Mo, Zhiyu Wang, Hua Chen, Faxin Yu

IEICE Electron. Express, 2024

2022

A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC.

Yu Liu, Mingliang Chen, Chenge Wang, Jiarui Liu, Zhiyu Wang, Hua Chen, Faxin Yu

IEICE Electron. Express, 2022