Jiarui Liu
Orcid: 0000-0002-1567-3422Affiliations:
- Zhejiang University, School of Aeronautics and Astronautics, Hangzhou, China (PhD 2014)
According to our database1,
Jiarui Liu
authored at least 17 papers
between 2013 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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Bibliography
2023
IEICE Electron. Express, 2023
A 0.1-1.9GHz 65nm CMOS variable-gain mixer-first receiver with DSA and noise-shaping TIA.
IEICE Electron. Express, 2023
An enhanced peak limited digital predistortion based on indirect learning architecture.
IEICE Electron. Express, 2023
A Frequency-Domain I/Q Imbalance Calibration Algorithm for Wideband Direct Conversion Receivers Using Low-Cost Compensator.
IEEE Access, 2023
2022
A Low Phase Noise VCO With Placement Reordered Cores and High-Q Bond Wire Array Inductors.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 14-Bit 3-GS/s DAC Achieving SFDR >63dB Up to 1.4GHz With Random Differential-Quad Switching Technique.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC.
IEICE Electron. Express, 2022
2021
A 14bit 500MS/s 85.62dBc SFDR 66.29dB SNDR SHA-less pipelined ADC with a stable and high-linearity input buffer and aperture-error calibration in 40nm CMOS.
IEICE Electron. Express, 2021
A 92 fs<sub>rms</sub> jitter frequency synthesizer based on a multicore class-C voltage-controlled oscillator with digital automatic amplitude control.
IEICE Electron. Express, 2021
2020
A highly linear 10 Gb/s MOS current mode logic driver with large output voltage swing based on an active inductor.
IEICE Electron. Express, 2020
2019
A 210fs RMS jitter 187.5 MHz-3GHz fractional-N frequency synthesizer with quantization noise suppression techniques and chopping differential charge pump for SDR applications.
Microelectron. J., 2019
An effective DC offset calibration method combined with analog and digital circuits for direct conversion receivers.
IEICE Electron. Express, 2019
A 0.07-3 GHz wideband front-end for SDR receiver with 2.3 dB NF and 12 dBm IIP<sub>3</sub> in 65 nm CMOS.
IEICE Electron. Express, 2019
A 14 bit 500 MS/s SHA-less pipelined ADC with a highly linear input buffer and power-efficient supply voltage domain arrangement in 40 nm CMOS.
IEICE Electron. Express, 2019
2018
IEICE Electron. Express, 2018
2017
J. Electr. Comput. Eng., 2017
2013
IEICE Trans. Inf. Syst., 2013